575 	struct clk_hw_onecell_data *clk_data;  in mtk_topckgen_init()  local
583 	clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);  in mtk_topckgen_init()
586 				    clk_data);  in mtk_topckgen_init()
589 				 clk_data);  in mtk_topckgen_init()
592 				    base, &mt7629_clk_lock, clk_data);  in mtk_topckgen_init()
594 	clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);  in mtk_topckgen_init()
595 	clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);  in mtk_topckgen_init()
596 	clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);  in mtk_topckgen_init()
598 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);  in mtk_topckgen_init()
604 	struct clk_hw_onecell_data *clk_data;  in mtk_infrasys_init()  local
606 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);  in mtk_infrasys_init()
609 			       clk_data);  in mtk_infrasys_init()
612 				  clk_data);  in mtk_infrasys_init()
615 				      clk_data);  in mtk_infrasys_init()
620 	struct clk_hw_onecell_data *clk_data;  in mtk_pericfg_init()  local
629 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);  in mtk_pericfg_init()
632 			       clk_data);  in mtk_pericfg_init()
635 				    &mt7629_clk_lock, clk_data);  in mtk_pericfg_init()
637 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);  in mtk_pericfg_init()
641 	clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);  in mtk_pericfg_init()
648 	struct clk_hw_onecell_data *clk_data;  in mtk_apmixedsys_init()  local
651 	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);  in mtk_apmixedsys_init()
652 	if (!clk_data)  in mtk_apmixedsys_init()
656 			      clk_data);  in mtk_apmixedsys_init()
659 			       ARRAY_SIZE(apmixed_clks), clk_data);  in mtk_apmixedsys_init()
661 	clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);  in mtk_apmixedsys_init()
662 	clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk);  in mtk_apmixedsys_init()
664 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);  in mtk_apmixedsys_init()