Lines Matching refs:clk_info
83 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_recalc_rate() local
90 BUG_ON(clk_info->type != CGU_CLK_PLL); in ingenic_pll_recalc_rate()
91 pll_info = &clk_info->pll; in ingenic_pll_recalc_rate()
147 ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, in ingenic_pll_calc() argument
151 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_calc()
175 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_round_rate() local
177 return ingenic_pll_calc(clk_info, req_rate, *prate, NULL, NULL, NULL); in ingenic_pll_round_rate()
196 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_set_rate() local
197 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_set_rate()
203 rate = ingenic_pll_calc(clk_info, req_rate, parent_rate, in ingenic_pll_set_rate()
207 clk_info->name, req_rate, rate); in ingenic_pll_set_rate()
236 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_enable() local
237 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_enable()
267 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_disable() local
268 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_disable()
285 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_is_enabled() local
286 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_is_enabled()
311 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_get_parent() local
316 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_get_parent()
317 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_get_parent()
318 hw_idx = (reg >> clk_info->mux.shift) & in ingenic_clk_get_parent()
319 GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_get_parent()
326 if (clk_info->parents[i] != -1) in ingenic_clk_get_parent()
337 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_set_parent() local
343 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_set_parent()
351 num_poss = 1 << clk_info->mux.bits; in ingenic_clk_set_parent()
353 if (clk_info->parents[hw_idx] == -1) in ingenic_clk_set_parent()
363 mask = GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_set_parent()
364 mask <<= clk_info->mux.shift; in ingenic_clk_set_parent()
369 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
371 reg |= hw_idx << clk_info->mux.shift; in ingenic_clk_set_parent()
372 writel(reg, cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
385 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_recalc_rate() local
391 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_recalc_rate()
394 if (!(clk_info->div.bypass_mask & BIT(parent))) { in ingenic_clk_recalc_rate()
395 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
396 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
397 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
399 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
400 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
402 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
406 } else if (clk_info->type & CGU_CLK_FIXDIV) { in ingenic_clk_recalc_rate()
407 rate /= clk_info->fixdiv.div; in ingenic_clk_recalc_rate()
414 ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info, in ingenic_clk_calc_hw_div() argument
419 for (i = 0; i < (1 << clk_info->div.bits) in ingenic_clk_calc_hw_div()
420 && clk_info->div.div_table[i]; i++) { in ingenic_clk_calc_hw_div()
421 if (clk_info->div.div_table[i] >= div && in ingenic_clk_calc_hw_div()
422 clk_info->div.div_table[i] < best) { in ingenic_clk_calc_hw_div()
423 best = clk_info->div.div_table[i]; in ingenic_clk_calc_hw_div()
436 const struct ingenic_cgu_clk_info *clk_info, in ingenic_clk_calc_div() argument
443 if (clk_info->div.bypass_mask & BIT(parent)) in ingenic_clk_calc_div()
449 if (clk_info->div.div_table) { in ingenic_clk_calc_div()
450 hw_div = ingenic_clk_calc_hw_div(clk_info, div); in ingenic_clk_calc_div()
452 return clk_info->div.div_table[hw_div]; in ingenic_clk_calc_div()
456 div = clamp_t(unsigned int, div, clk_info->div.div, in ingenic_clk_calc_div()
457 clk_info->div.div << clk_info->div.bits); in ingenic_clk_calc_div()
464 div = DIV_ROUND_UP(div, clk_info->div.div); in ingenic_clk_calc_div()
465 div *= clk_info->div.div; in ingenic_clk_calc_div()
475 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_round_rate() local
478 if (clk_info->type & CGU_CLK_DIV) in ingenic_clk_round_rate()
479 div = ingenic_clk_calc_div(hw, clk_info, *parent_rate, req_rate); in ingenic_clk_round_rate()
480 else if (clk_info->type & CGU_CLK_FIXDIV) in ingenic_clk_round_rate()
481 div = clk_info->fixdiv.div; in ingenic_clk_round_rate()
489 const struct ingenic_cgu_clk_info *clk_info) in ingenic_clk_check_stable() argument
493 return readl_poll_timeout(cgu->base + clk_info->div.reg, reg, in ingenic_clk_check_stable()
494 !(reg & BIT(clk_info->div.busy_bit)), in ingenic_clk_check_stable()
503 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_set_rate() local
510 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_set_rate()
511 div = ingenic_clk_calc_div(hw, clk_info, parent_rate, req_rate); in ingenic_clk_set_rate()
517 if (clk_info->div.div_table) in ingenic_clk_set_rate()
518 hw_div = ingenic_clk_calc_hw_div(clk_info, div); in ingenic_clk_set_rate()
520 hw_div = ((div / clk_info->div.div) - 1); in ingenic_clk_set_rate()
523 reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
526 mask = GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_set_rate()
527 reg &= ~(mask << clk_info->div.shift); in ingenic_clk_set_rate()
528 reg |= hw_div << clk_info->div.shift; in ingenic_clk_set_rate()
531 if (clk_info->div.stop_bit != -1) in ingenic_clk_set_rate()
532 reg &= ~BIT(clk_info->div.stop_bit); in ingenic_clk_set_rate()
535 if (clk_info->div.ce_bit != -1) in ingenic_clk_set_rate()
536 reg |= BIT(clk_info->div.ce_bit); in ingenic_clk_set_rate()
539 writel(reg, cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
542 if (clk_info->div.busy_bit != -1) in ingenic_clk_set_rate()
543 ret = ingenic_clk_check_stable(cgu, clk_info); in ingenic_clk_set_rate()
555 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_enable() local
559 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_enable()
562 ingenic_cgu_gate_set(cgu, &clk_info->gate, false); in ingenic_clk_enable()
565 if (clk_info->gate.delay_us) in ingenic_clk_enable()
566 udelay(clk_info->gate.delay_us); in ingenic_clk_enable()
575 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_disable() local
579 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_disable()
582 ingenic_cgu_gate_set(cgu, &clk_info->gate, true); in ingenic_clk_disable()
590 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_is_enabled() local
594 if (clk_info->type & CGU_CLK_GATE) in ingenic_clk_is_enabled()
595 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); in ingenic_clk_is_enabled()
619 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx]; in ingenic_register_clock() local
627 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names)); in ingenic_register_clock()
629 if (clk_info->type == CGU_CLK_EXT) { in ingenic_register_clock()
630 clk = of_clk_get_by_name(cgu->np, clk_info->name); in ingenic_register_clock()
633 __func__, clk_info->name); in ingenic_register_clock()
637 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()
646 if (!clk_info->type) { in ingenic_register_clock()
648 clk_info->name); in ingenic_register_clock()
662 clk_init.name = clk_info->name; in ingenic_register_clock()
663 clk_init.flags = clk_info->flags; in ingenic_register_clock()
666 caps = clk_info->type; in ingenic_register_clock()
679 num_possible = 1 << clk_info->mux.bits; in ingenic_register_clock()
681 num_possible = ARRAY_SIZE(clk_info->parents); in ingenic_register_clock()
684 if (clk_info->parents[i] == -1) in ingenic_register_clock()
687 parent = cgu->clocks.clks[clk_info->parents[i]]; in ingenic_register_clock()
696 BUG_ON(clk_info->parents[0] == -1); in ingenic_register_clock()
698 parent = cgu->clocks.clks[clk_info->parents[0]]; in ingenic_register_clock()
703 clk_init.ops = clk_info->custom.clk_ops; in ingenic_register_clock()
744 clk_info->name); in ingenic_register_clock()
749 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()