115 				unsigned long parent_rate)  in vt8500_dclk_recalc_rate()  argument
128 	return parent_rate / div;  in vt8500_dclk_recalc_rate()
158 				unsigned long parent_rate)  in vt8500_dclk_set_rate()  argument
167 	divisor =  parent_rate / rate;  in vt8500_dclk_set_rate()
350 static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,  in vt8500_find_pll_bits()  argument
356 	if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {  in vt8500_find_pll_bits()
362 	if (rate <= parent_rate * 31)  in vt8500_find_pll_bits()
368 	*multiplier = rate / (parent_rate / *prediv);  in vt8500_find_pll_bits()
369 	tclk = (parent_rate / *prediv) * *multiplier;  in vt8500_find_pll_bits()
390 	unsigned long parent_rate, u32 *multiplier, u32 *divisor1,  in wm8650_find_pll_bits()  argument
395 	if (!parent_rate || (rate < 37500000) || (rate > 600000000))  in wm8650_find_pll_bits()
407 		rate_err = O1 % parent_rate;  in wm8650_find_pll_bits()
409 			*multiplier = O1 / parent_rate;  in wm8650_find_pll_bits()
425 static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)  in wm8750_get_filter()  argument
428 	u32 freq = (parent_rate / 1000000) / (divisor1 + 1);  in wm8750_get_filter()
452 static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,  in wm8750_find_pll_bits()  argument
465 				tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));  in wm8750_find_pll_bits()
471 					*filter = wm8750_get_filter(parent_rate, div1);  in wm8750_find_pll_bits()
495 	*filter = wm8750_get_filter(parent_rate, *divisor1);  in wm8750_find_pll_bits()
500 static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,  in wm8850_find_pll_bits()  argument
513 				tclk = parent_rate * ((mul + 1) * 2) /  in wm8850_find_pll_bits()
547 				unsigned long parent_rate)  in vtwm_pll_set_rate()  argument
559 		ret = vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);  in vtwm_pll_set_rate()
564 		ret = wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);  in vtwm_pll_set_rate()
569 		ret = wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);  in vtwm_pll_set_rate()
574 		ret = wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);  in vtwm_pll_set_rate()
637 				unsigned long parent_rate)  in vtwm_pll_recalc_rate()  argument
645 		pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);  in vtwm_pll_recalc_rate()
649 		pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);  in vtwm_pll_recalc_rate()
653 		pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);  in vtwm_pll_recalc_rate()
657 		pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);  in vtwm_pll_recalc_rate()