379 	struct m10v_clk_divider *divider = to_m10v_div(hw);  in m10v_clk_divider_recalc_rate()  local
382 	val = readl(divider->reg) >> divider->shift;  in m10v_clk_divider_recalc_rate()
383 	val &= clk_div_mask(divider->width);  in m10v_clk_divider_recalc_rate()
385 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in m10v_clk_divider_recalc_rate()
386 				   divider->flags, divider->width);  in m10v_clk_divider_recalc_rate()
392 	struct m10v_clk_divider *divider = to_m10v_div(hw);  in m10v_clk_divider_round_rate()  local
395 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in m10v_clk_divider_round_rate()
398 		val = readl(divider->reg) >> divider->shift;  in m10v_clk_divider_round_rate()
399 		val &= clk_div_mask(divider->width);  in m10v_clk_divider_round_rate()
401 		return divider_ro_round_rate(hw, rate, prate, divider->table,  in m10v_clk_divider_round_rate()
402 					     divider->width, divider->flags,  in m10v_clk_divider_round_rate()
406 	return divider_round_rate(hw, rate, prate, divider->table,  in m10v_clk_divider_round_rate()
407 				  divider->width, divider->flags);  in m10v_clk_divider_round_rate()
413 	struct m10v_clk_divider *divider = to_m10v_div(hw);  in m10v_clk_divider_set_rate()  local
417 	u32 write_en = BIT(divider->width - 1);  in m10v_clk_divider_set_rate()
419 	value = divider_get_val(rate, parent_rate, divider->table,  in m10v_clk_divider_set_rate()
420 				divider->width, divider->flags);  in m10v_clk_divider_set_rate()
424 	if (divider->lock)  in m10v_clk_divider_set_rate()
425 		spin_lock_irqsave(divider->lock, flags);  in m10v_clk_divider_set_rate()
427 		__acquire(divider->lock);  in m10v_clk_divider_set_rate()
429 	val = readl(divider->reg);  in m10v_clk_divider_set_rate()
430 	val &= ~(clk_div_mask(divider->width) << divider->shift);  in m10v_clk_divider_set_rate()
432 	val |= ((u32)value | write_en) << divider->shift;  in m10v_clk_divider_set_rate()
433 	writel(val, divider->reg);  in m10v_clk_divider_set_rate()
435 	if (divider->write_valid_reg) {  in m10v_clk_divider_set_rate()
436 		writel(M10V_DCHREQ, divider->write_valid_reg);  in m10v_clk_divider_set_rate()
437 		if (readl_poll_timeout(divider->write_valid_reg, val,  in m10v_clk_divider_set_rate()
443 	if (divider->lock)  in m10v_clk_divider_set_rate()
444 		spin_unlock_irqrestore(divider->lock, flags);  in m10v_clk_divider_set_rate()
446 		__release(divider->lock);  in m10v_clk_divider_set_rate()