29 static inline u32 clk_div_readl(struct clk_divider *divider)  in clk_div_readl()  argument
31 	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)  in clk_div_readl()
32 		return ioread32be(divider->reg);  in clk_div_readl()
34 	return readl(divider->reg);  in clk_div_readl()
37 static inline void clk_div_writel(struct clk_divider *divider, u32 val)  in clk_div_writel()  argument
39 	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)  in clk_div_writel()
40 		iowrite32be(val, divider->reg);  in clk_div_writel()
42 		writel(val, divider->reg);  in clk_div_writel()
152 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_recalc_rate()  local
155 	val = clk_div_readl(divider) >> divider->shift;  in clk_divider_recalc_rate()
156 	val &= clk_div_mask(divider->width);  in clk_divider_recalc_rate()
158 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in clk_divider_recalc_rate()
159 				   divider->flags, divider->width);  in clk_divider_recalc_rate()
431 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_round_rate()  local
434 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in clk_divider_round_rate()
437 		val = clk_div_readl(divider) >> divider->shift;  in clk_divider_round_rate()
438 		val &= clk_div_mask(divider->width);  in clk_divider_round_rate()
440 		return divider_ro_round_rate(hw, rate, prate, divider->table,  in clk_divider_round_rate()
441 					     divider->width, divider->flags,  in clk_divider_round_rate()
445 	return divider_round_rate(hw, rate, prate, divider->table,  in clk_divider_round_rate()
446 				  divider->width, divider->flags);  in clk_divider_round_rate()
452 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_determine_rate()  local
455 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in clk_divider_determine_rate()
458 		val = clk_div_readl(divider) >> divider->shift;  in clk_divider_determine_rate()
459 		val &= clk_div_mask(divider->width);  in clk_divider_determine_rate()
461 		return divider_ro_determine_rate(hw, req, divider->table,  in clk_divider_determine_rate()
462 						 divider->width,  in clk_divider_determine_rate()
463 						 divider->flags, val);  in clk_divider_determine_rate()
466 	return divider_determine_rate(hw, req, divider->table, divider->width,  in clk_divider_determine_rate()
467 				      divider->flags);  in clk_divider_determine_rate()
490 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_set_rate()  local
495 	value = divider_get_val(rate, parent_rate, divider->table,  in clk_divider_set_rate()
496 				divider->width, divider->flags);  in clk_divider_set_rate()
500 	if (divider->lock)  in clk_divider_set_rate()
501 		spin_lock_irqsave(divider->lock, flags);  in clk_divider_set_rate()
503 		__acquire(divider->lock);  in clk_divider_set_rate()
505 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {  in clk_divider_set_rate()
506 		val = clk_div_mask(divider->width) << (divider->shift + 16);  in clk_divider_set_rate()
508 		val = clk_div_readl(divider);  in clk_divider_set_rate()
509 		val &= ~(clk_div_mask(divider->width) << divider->shift);  in clk_divider_set_rate()
511 	val |= (u32)value << divider->shift;  in clk_divider_set_rate()
512 	clk_div_writel(divider, val);  in clk_divider_set_rate()
514 	if (divider->lock)  in clk_divider_set_rate()
515 		spin_unlock_irqrestore(divider->lock, flags);  in clk_divider_set_rate()
517 		__release(divider->lock);  in clk_divider_set_rate()