Lines Matching refs:CHB
240 #define CHB 0x40 /* channel B offset */ macro
343 write_reg16(info, CHB + IMR, info->imrb_value); in irq_disable()
353 write_reg16(info, CHB + IMR, info->imrb_value); in irq_enable()
1049 irq_disable(info, CHB, IRQ_CTS); in cts_change()
1084 irq_disable(info, CHB, IRQ_DCD); in dcd_change()
1184 isr = read_reg16(info, CHB + ISR); in mgslpc_isr()
1387 irq_enable(info, CHB, IRQ_DCD | IRQ_CTS); in mgslpc_program_hw()
2919 write_reg(info, CHB + MODE, val); in enable_auxclk()
2931 write_reg(info, CHB + CCR0, 0xc0); in enable_auxclk()
2944 write_reg(info, CHB + CCR1, 0x17); in enable_auxclk()
2959 write_reg(info, CHB + CCR2, 0x38); in enable_auxclk()
2961 write_reg(info, CHB + CCR2, 0x30); in enable_auxclk()
2974 write_reg(info, CHB + CCR4, 0x50); in enable_auxclk()
2980 mgslpc_set_rate(info, CHB, info->params.clock_speed); in enable_auxclk()
2982 mgslpc_set_rate(info, CHB, 921600); in enable_auxclk()
3015 irq_disable(info, CHB, 0xffff); in hdlc_mode()
3216 irq_enable(info, CHB, IRQ_CTS); in hdlc_mode()
3333 write_reg(info, CHB + CCR0, 0x80); in reset_device()
3335 write_reg(info, CHB + MODE, 0); in reset_device()
3339 irq_disable(info, CHB, 0xffff); in reset_device()
3385 irq_disable(info, CHB, 0xffff); in async_mode()
3535 irq_enable(info, CHB, IRQ_CTS); in async_mode()
3568 if (read_reg(info, CHB + VSTR) & BIT7) in get_signals()
3570 if (read_reg(info, CHB + STAR) & BIT1) in get_signals()