3153 #undef ZERO
3154 #define ZERO(reg) writel(0, port_mmio + (reg))  macro
3162 	ZERO(0x028);	/* command */  in mv5_reset_hc_port()
3164 	ZERO(0x004);	/* timer */  in mv5_reset_hc_port()
3165 	ZERO(0x008);	/* irq err cause */  in mv5_reset_hc_port()
3166 	ZERO(0x00c);	/* irq err mask */  in mv5_reset_hc_port()
3167 	ZERO(0x010);	/* rq bah */  in mv5_reset_hc_port()
3168 	ZERO(0x014);	/* rq inp */  in mv5_reset_hc_port()
3169 	ZERO(0x018);	/* rq outp */  in mv5_reset_hc_port()
3170 	ZERO(0x01c);	/* respq bah */  in mv5_reset_hc_port()
3171 	ZERO(0x024);	/* respq outp */  in mv5_reset_hc_port()
3172 	ZERO(0x020);	/* respq inp */  in mv5_reset_hc_port()
3173 	ZERO(0x02c);	/* test control */  in mv5_reset_hc_port()
3176 #undef ZERO
3178 #define ZERO(reg) writel(0, hc_mmio + (reg))  macro
3185 	ZERO(0x00c);  in mv5_reset_one_hc()
3186 	ZERO(0x010);  in mv5_reset_one_hc()
3187 	ZERO(0x014);  in mv5_reset_one_hc()
3188 	ZERO(0x018);  in mv5_reset_one_hc()
3195 #undef ZERO
3214 #undef ZERO
3215 #define ZERO(reg) writel(0, mmio + (reg))  macro
3225 	ZERO(MV_PCI_DISC_TIMER);  in mv_reset_pci_bus()
3226 	ZERO(MV_PCI_MSI_TRIGGER);  in mv_reset_pci_bus()
3228 	ZERO(MV_PCI_SERR_MASK);  in mv_reset_pci_bus()
3229 	ZERO(hpriv->irq_cause_offset);  in mv_reset_pci_bus()
3230 	ZERO(hpriv->irq_mask_offset);  in mv_reset_pci_bus()
3231 	ZERO(MV_PCI_ERR_LOW_ADDRESS);  in mv_reset_pci_bus()
3232 	ZERO(MV_PCI_ERR_HIGH_ADDRESS);  in mv_reset_pci_bus()
3233 	ZERO(MV_PCI_ERR_ATTRIBUTE);  in mv_reset_pci_bus()
3234 	ZERO(MV_PCI_ERR_COMMAND);  in mv_reset_pci_bus()
3236 #undef ZERO
3436 #undef ZERO
3437 #define ZERO(reg) writel(0, port_mmio + (reg))  macro
3445 	ZERO(0x028);		/* command */  in mv_soc_reset_hc_port()
3447 	ZERO(0x004);		/* timer */  in mv_soc_reset_hc_port()
3448 	ZERO(0x008);		/* irq err cause */  in mv_soc_reset_hc_port()
3449 	ZERO(0x00c);		/* irq err mask */  in mv_soc_reset_hc_port()
3450 	ZERO(0x010);		/* rq bah */  in mv_soc_reset_hc_port()
3451 	ZERO(0x014);		/* rq inp */  in mv_soc_reset_hc_port()
3452 	ZERO(0x018);		/* rq outp */  in mv_soc_reset_hc_port()
3453 	ZERO(0x01c);		/* respq bah */  in mv_soc_reset_hc_port()
3454 	ZERO(0x024);		/* respq outp */  in mv_soc_reset_hc_port()
3455 	ZERO(0x020);		/* respq inp */  in mv_soc_reset_hc_port()
3456 	ZERO(0x02c);		/* test control */  in mv_soc_reset_hc_port()
3460 #undef ZERO
3462 #define ZERO(reg) writel(0, hc_mmio + (reg))  macro
3468 	ZERO(0x00c);  in mv_soc_reset_one_hc()
3469 	ZERO(0x010);  in mv_soc_reset_one_hc()
3470 	ZERO(0x014);  in mv_soc_reset_one_hc()
3474 #undef ZERO