Lines Matching refs:div4_clks
64 struct clk div4_clks[DIV4_NR] = { variable
83 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
84 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
85 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
86 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
87 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
88 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
89 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
90 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
91 [MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
92 [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
106 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
107 CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]),
108 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
109 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
110 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
111 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
142 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), in arch_clk_init()