174 	switch (in_be64(&priv2->mfc_control_RW) &  in save_mfc_cntl()
177 		POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &  in save_mfc_cntl()
183 			csa->priv2.mfc_control_RW =  in save_mfc_cntl()
184 				in_be64(&priv2->mfc_control_RW) |  in save_mfc_cntl()
188 		out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);  in save_mfc_cntl()
189 		POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &  in save_mfc_cntl()
193 			csa->priv2.mfc_control_RW =  in save_mfc_cntl()
194 				in_be64(&priv2->mfc_control_RW) &  in save_mfc_cntl()
259 	csa->priv2.mfc_control_RW &= ~mask;  in save_mfc_stopped_status()
260 	csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask;  in save_mfc_stopped_status()
271 	out_be64(&priv2->mfc_control_RW,  in halt_mfc_decr()
342 	if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {  in save_mfc_queues()
464 	out_be64(&priv2->mfc_control_RW,  in purge_mfc_queue()
478 	POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &  in wait_purge_complete()
700 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);  in resume_mfc_queue()
736 		csa->priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;  in set_switch_active()
970 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |  in suspend_mfc_and_halt_decr()
984 	POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &  in wait_suspend_mfc_complete()
1263 	if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {  in setup_decr()
1392 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);  in suspend_mfc()
1425 	if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {  in restore_mfc_queues()
1732 	out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);  in restore_mfc_cntl()
2166 	csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |  in init_priv2()