Lines Matching refs:CPM_PORTE
60 {CPM_PORTE, 21, CPM_PIN_INPUT}, /* RX */
61 {CPM_PORTE, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
69 {CPM_PORTE, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
70 {CPM_PORTE, 17, CPM_PIN_INPUT}, /* CLK5 */
71 {CPM_PORTE, 16, CPM_PIN_INPUT}, /* CLK6 */
85 {CPM_PORTE, 30, CPM_PIN_OUTPUT},
86 {CPM_PORTE, 31, CPM_PIN_OUTPUT},
90 {CPM_PORTE, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
91 {CPM_PORTE, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
92 {CPM_PORTE, 16, CPM_PIN_OUTPUT},
93 {CPM_PORTE, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
94 {CPM_PORTE, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
95 {CPM_PORTE, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
96 {CPM_PORTE, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
97 {CPM_PORTE, 21, CPM_PIN_OUTPUT},
98 {CPM_PORTE, 22, CPM_PIN_OUTPUT},
99 {CPM_PORTE, 23, CPM_PIN_OUTPUT},
100 {CPM_PORTE, 24, CPM_PIN_OUTPUT},
101 {CPM_PORTE, 25, CPM_PIN_OUTPUT},
102 {CPM_PORTE, 26, CPM_PIN_OUTPUT},
103 {CPM_PORTE, 27, CPM_PIN_OUTPUT},
104 {CPM_PORTE, 28, CPM_PIN_OUTPUT},
105 {CPM_PORTE, 29, CPM_PIN_OUTPUT},