62 #define IS_LE	1  macro
65 #define IS_LE	0  macro
739 		err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);  in emulate_lq()
765 	err = write_mem(vals[IS_LE], ea, 8, regs);  in emulate_stq()
793 		if (IS_LE && (op->vsx_flags & VSX_LDLEFT))  in emulate_vsx_load()
801 		i = IS_LE ? 8 : 8 - read_size;  in emulate_vsx_load()
808 				reg->d[IS_LE] = (signed int) reg->d[IS_LE];  in emulate_vsx_load()
811 				conv_sp_to_dp(&reg->fp[1 + IS_LE],  in emulate_vsx_load()
812 					      &reg->dp[IS_LE]);  in emulate_vsx_load()
820 				reg->d[IS_BE] = reg->d[IS_LE];  in emulate_vsx_load()
827 			i = IS_LE ? 3 - j : j;  in emulate_vsx_load()
831 			u32 val = reg->w[IS_LE ? 3 : 0];  in emulate_vsx_load()
833 				i = IS_LE ? 3 - j : j;  in emulate_vsx_load()
842 			i = IS_LE ? 7 - j : j;  in emulate_vsx_load()
850 			i = IS_LE ? 15 - j : j;  in emulate_vsx_load()
892 		if (IS_LE && (op->vsx_flags & VSX_LDLEFT))  in emulate_vsx_store()
905 		i = IS_LE ? 8 : 8 - write_size;  in emulate_vsx_store()
909 			conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);  in emulate_vsx_store()
926 			i = IS_LE ? 3 - j : j;  in emulate_vsx_store()
934 			i = IS_LE ? 7 - j : j;  in emulate_vsx_store()
942 			i = IS_LE ? 15 - j : j;  in emulate_vsx_store()
971 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_load()
976 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_load()
984 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_load()
989 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_load()
1017 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_store()
1022 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_store()
1030 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_store()
1035 				j = IS_LE ? nr_vsx_regs - i - 1 : i;  in do_vsx_store()