Lines Matching refs:r4
70 ld r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
80 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
94 neg r6,r4
99 err1; lbz r0,0(r4)
100 addi r4,r4,1
105 err1; lhz r0,0(r4)
106 addi r4,r4,2
111 err1; lwz r0,0(r4)
112 addi r4,r4,4
139 err2; ld r0,0(r4)
140 err2; ld r6,8(r4)
141 err2; ld r7,16(r4)
142 err2; ld r8,24(r4)
143 err2; ld r9,32(r4)
144 err2; ld r10,40(r4)
145 err2; ld r11,48(r4)
146 err2; ld r12,56(r4)
147 err2; ld r14,64(r4)
148 err2; ld r15,72(r4)
149 err2; ld r16,80(r4)
150 err2; ld r17,88(r4)
151 err2; ld r18,96(r4)
152 err2; ld r19,104(r4)
153 err2; ld r20,112(r4)
154 err2; ld r21,120(r4)
155 addi r4,r4,128
193 err1; ld r0,0(r4)
194 err1; ld r6,8(r4)
195 err1; ld r7,16(r4)
196 err1; ld r8,24(r4)
197 err1; ld r9,32(r4)
198 err1; ld r10,40(r4)
199 err1; ld r11,48(r4)
200 err1; ld r12,56(r4)
201 addi r4,r4,64
214 err1; ld r0,0(r4)
215 err1; ld r6,8(r4)
216 err1; ld r7,16(r4)
217 err1; ld r8,24(r4)
218 addi r4,r4,32
227 err1; ld r0,0(r4)
228 err1; ld r6,8(r4)
229 addi r4,r4,16
240 err1; lwz r0,0(r4) /* Less chance of a reject with word ops */
241 err1; lwz r6,4(r4)
242 addi r4,r4,8
248 err1; lwz r0,0(r4)
249 addi r4,r4,4
254 err1; lhz r0,0(r4)
255 addi r4,r4,2
260 err1; lbz r0,0(r4)
279 ld r4,STK_REG(R30)(r1)
288 clrrdi r6,r4,7
319 xor r6,r4,r3
329 err3; lbz r0,0(r4)
330 addi r4,r4,1
335 err3; lhz r0,0(r4)
336 addi r4,r4,2
341 err3; lwz r0,0(r4)
342 addi r4,r4,4
347 err3; ld r0,0(r4)
348 addi r4,r4,8
365 err3; lvx v1,0,r4
366 addi r4,r4,16
371 err3; lvx v1,0,r4
372 err3; lvx v0,r4,r9
373 addi r4,r4,32
379 err3; lvx v3,0,r4
380 err3; lvx v2,r4,r9
381 err3; lvx v1,r4,r10
382 err3; lvx v0,r4,r11
383 addi r4,r4,64
410 err4; lvx v7,0,r4
411 err4; lvx v6,r4,r9
412 err4; lvx v5,r4,r10
413 err4; lvx v4,r4,r11
414 err4; lvx v3,r4,r12
415 err4; lvx v2,r4,r14
416 err4; lvx v1,r4,r15
417 err4; lvx v0,r4,r16
418 addi r4,r4,128
440 err3; lvx v3,0,r4
441 err3; lvx v2,r4,r9
442 err3; lvx v1,r4,r10
443 err3; lvx v0,r4,r11
444 addi r4,r4,64
452 err3; lvx v1,0,r4
453 err3; lvx v0,r4,r9
454 addi r4,r4,32
460 err3; lvx v1,0,r4
461 addi r4,r4,16
469 err3; ld r0,0(r4)
470 addi r4,r4,8
475 err3; lwz r0,0(r4)
476 addi r4,r4,4
481 err3; lhz r0,0(r4)
482 addi r4,r4,2
487 err3; lbz r0,0(r4)
500 err3; lbz r0,0(r4)
501 addi r4,r4,1
506 err3; lhz r0,0(r4)
507 addi r4,r4,2
512 err3; lwz r0,0(r4)
513 addi r4,r4,4
518 err3; lwz r0,0(r4) /* Less chance of a reject with word ops */
519 err3; lwz r7,4(r4)
520 addi r4,r4,8
537 LVS(v16,0,r4) /* Setup permute control vector */
538 err3; lvx v0,0,r4
539 addi r4,r4,16
542 err3; lvx v1,0,r4
544 addi r4,r4,16
550 err3; lvx v1,0,r4
552 err3; lvx v0,r4,r9
554 addi r4,r4,32
560 err3; lvx v3,0,r4
562 err3; lvx v2,r4,r9
564 err3; lvx v1,r4,r10
566 err3; lvx v0,r4,r11
568 addi r4,r4,64
595 err4; lvx v7,0,r4
597 err4; lvx v6,r4,r9
599 err4; lvx v5,r4,r10
601 err4; lvx v4,r4,r11
603 err4; lvx v3,r4,r12
605 err4; lvx v2,r4,r14
607 err4; lvx v1,r4,r15
609 err4; lvx v0,r4,r16
611 addi r4,r4,128
633 err3; lvx v3,0,r4
635 err3; lvx v2,r4,r9
637 err3; lvx v1,r4,r10
639 err3; lvx v0,r4,r11
641 addi r4,r4,64
649 err3; lvx v1,0,r4
651 err3; lvx v0,r4,r9
653 addi r4,r4,32
659 err3; lvx v1,0,r4
661 addi r4,r4,16
667 addi r4,r4,-16 /* Unwind the +16 load offset */
670 err3; lwz r0,0(r4) /* Less chance of a reject with word ops */
671 err3; lwz r6,4(r4)
672 addi r4,r4,8
678 err3; lwz r0,0(r4)
679 addi r4,r4,4
684 err3; lhz r0,0(r4)
685 addi r4,r4,2
690 err3; lbz r0,0(r4)