128 static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
281 static inline void IRQ_setbit(struct irq_queue *q, int n_IRQ)  in IRQ_setbit()  argument
283 	set_bit(n_IRQ, q->queue);  in IRQ_setbit()
286 static inline void IRQ_resetbit(struct irq_queue *q, int n_IRQ)  in IRQ_resetbit()  argument
288 	clear_bit(n_IRQ, q->queue);  in IRQ_resetbit()
323 static void IRQ_local_pipe(struct openpic *opp, int n_CPU, int n_IRQ,  in IRQ_local_pipe()  argument
331 	src = &opp->src[n_IRQ];  in IRQ_local_pipe()
334 		__func__, n_IRQ, active, was_active);  in IRQ_local_pipe()
338 			__func__, src->output, n_IRQ, active, was_active,  in IRQ_local_pipe()
349 					__func__, src->output, n_CPU, n_IRQ);  in IRQ_local_pipe()
356 					__func__, src->output, n_CPU, n_IRQ);  in IRQ_local_pipe()
370 		IRQ_setbit(&dst->raised, n_IRQ);  in IRQ_local_pipe()
372 		IRQ_resetbit(&dst->raised, n_IRQ);  in IRQ_local_pipe()
378 			__func__, n_IRQ, priority, dst->ctpr, n_CPU);  in IRQ_local_pipe()
386 				__func__, n_IRQ, dst->servicing.next, n_CPU);  in IRQ_local_pipe()
389 				__func__, n_CPU, n_IRQ, dst->raised.next);  in IRQ_local_pipe()
397 				__func__, n_IRQ, dst->raised.next,  in IRQ_local_pipe()
403 				__func__, n_IRQ, dst->ctpr,  in IRQ_local_pipe()
411 static void openpic_update_irq(struct openpic *opp, int n_IRQ)  in openpic_update_irq()  argument
417 	src = &opp->src[n_IRQ];  in openpic_update_irq()
422 		pr_debug("%s: IRQ %d is disabled\n", __func__, n_IRQ);  in openpic_update_irq()
433 		pr_debug("%s: IRQ %d is already inactive\n", __func__, n_IRQ);  in openpic_update_irq()
444 		pr_debug("%s: IRQ %d has no target\n", __func__, n_IRQ);  in openpic_update_irq()
450 		IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active);  in openpic_update_irq()
455 				IRQ_local_pipe(opp, i, n_IRQ, active,  in openpic_update_irq()
466 				IRQ_local_pipe(opp, i, n_IRQ, active,  in openpic_update_irq()
475 static void openpic_set_irq(void *opaque, int n_IRQ, int level)  in openpic_set_irq()  argument
480 	if (n_IRQ >= MAX_IRQ) {  in openpic_set_irq()
481 		WARN_ONCE(1, "%s: IRQ %d out of range\n", __func__, n_IRQ);  in openpic_set_irq()
485 	src = &opp->src[n_IRQ];  in openpic_set_irq()
487 		n_IRQ, level, src->ivpr);  in openpic_set_irq()
491 		openpic_update_irq(opp, n_IRQ);  in openpic_set_irq()
496 			openpic_update_irq(opp, n_IRQ);  in openpic_set_irq()
507 			openpic_update_irq(opp, n_IRQ);  in openpic_set_irq()
561 static inline uint32_t read_IRQreg_idr(struct openpic *opp, int n_IRQ)  in read_IRQreg_idr()  argument
563 	return opp->src[n_IRQ].idr;  in read_IRQreg_idr()
566 static inline uint32_t read_IRQreg_ilr(struct openpic *opp, int n_IRQ)  in read_IRQreg_ilr()  argument
569 		return opp->src[n_IRQ].output;  in read_IRQreg_ilr()
574 static inline uint32_t read_IRQreg_ivpr(struct openpic *opp, int n_IRQ)  in read_IRQreg_ivpr()  argument
576 	return opp->src[n_IRQ].ivpr;  in read_IRQreg_ivpr()
579 static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,  in write_IRQreg_idr()  argument
582 	struct irq_source *src = &opp->src[n_IRQ];  in write_IRQreg_idr()
595 	pr_debug("Set IDR %d to 0x%08x\n", n_IRQ, src->idr);  in write_IRQreg_idr()
624 static inline void write_IRQreg_ilr(struct openpic *opp, int n_IRQ,  in write_IRQreg_ilr()  argument
628 		struct irq_source *src = &opp->src[n_IRQ];  in write_IRQreg_ilr()
631 		pr_debug("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr,  in write_IRQreg_ilr()
638 static inline void write_IRQreg_ivpr(struct openpic *opp, int n_IRQ,  in write_IRQreg_ivpr()  argument
650 	opp->src[n_IRQ].ivpr =  in write_IRQreg_ivpr()
651 	    (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);  in write_IRQreg_ivpr()
657 	switch (opp->src[n_IRQ].type) {  in write_IRQreg_ivpr()
659 		opp->src[n_IRQ].level =  in write_IRQreg_ivpr()
660 		    !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK);  in write_IRQreg_ivpr()
664 		opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK;  in write_IRQreg_ivpr()
668 		opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK);  in write_IRQreg_ivpr()
672 	openpic_update_irq(opp, n_IRQ);  in write_IRQreg_ivpr()
673 	pr_debug("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val,  in write_IRQreg_ivpr()
674 		opp->src[n_IRQ].ivpr);  in write_IRQreg_ivpr()
1029 	int s_IRQ, n_IRQ;  in openpic_cpu_write_internal()  local
1095 		n_IRQ = IRQ_get_next(opp, &dst->raised);  in openpic_cpu_write_internal()
1096 		src = &opp->src[n_IRQ];  in openpic_cpu_write_internal()
1097 		if (n_IRQ != -1 &&  in openpic_cpu_write_internal()
1101 				idx, n_IRQ);  in openpic_cpu_write_internal()