Lines Matching refs:r4
47 mtspr \scratch , r4
48 mfspr r4, SPRN_SPRG_THREAD
49 lwz r4, THREAD_KVM_VCPU(r4)
50 stw r3, VCPU_GPR(R3)(r4)
51 stw r5, VCPU_GPR(R5)(r4)
52 stw r6, VCPU_GPR(R6)(r4)
55 stw r3, VCPU_GPR(R4)(r4)
56 stw r5, VCPU_CTR(r4)
59 stw r3, VCPU_PC(r4)
73 mtspr \scratch, r4
74 mfspr r4, SPRN_SPRG_THREAD
75 lwz r4, THREAD_KVM_VCPU(r4)
76 stw r3, VCPU_CRIT_SAVE(r4)
78 mfspr r4, SPRN_CSRR1
79 andi. r4, r4, MSR_PR
82 mfspr r4, SPRN_CSRR1
83 rlwinm r4, r4, 0, ~MSR_DE
84 mtspr SPRN_CSRR1, r4
85 lis r4, 0xffff
86 ori r4, r4, 0xffff
87 mtspr SPRN_DBSR, r4
88 mfspr r4, SPRN_SPRG_THREAD
89 lwz r4, THREAD_KVM_VCPU(r4)
91 lwz r3, VCPU_CRIT_SAVE(r4)
92 mfspr r4, \scratch
96 mfspr r4, SPRN_SPRG_THREAD
97 lwz r4, THREAD_KVM_VCPU(r4)
98 lwz r3, VCPU_CRIT_SAVE(r4)
99 mfspr r4, \scratch
140 stw r3, VCPU_CR(r4)
141 stw r7, VCPU_GPR(R7)(r4)
142 stw r8, VCPU_GPR(R8)(r4)
143 stw r9, VCPU_GPR(R9)(r4)
156 stw r8, VCPU_TIMING_EXIT_TBL(r4)
157 stw r9, VCPU_TIMING_EXIT_TBU(r4)
171 stw r9, VCPU_LAST_INST(r4)
173 stw r15, VCPU_GPR(R15)(r4)
174 stw r16, VCPU_GPR(R16)(r4)
175 stw r17, VCPU_GPR(R17)(r4)
176 stw r18, VCPU_GPR(R18)(r4)
177 stw r19, VCPU_GPR(R19)(r4)
178 stw r20, VCPU_GPR(R20)(r4)
179 stw r21, VCPU_GPR(R21)(r4)
180 stw r22, VCPU_GPR(R22)(r4)
181 stw r23, VCPU_GPR(R23)(r4)
182 stw r24, VCPU_GPR(R24)(r4)
183 stw r25, VCPU_GPR(R25)(r4)
184 stw r26, VCPU_GPR(R26)(r4)
185 stw r27, VCPU_GPR(R27)(r4)
186 stw r28, VCPU_GPR(R28)(r4)
187 stw r29, VCPU_GPR(R29)(r4)
188 stw r30, VCPU_GPR(R30)(r4)
189 stw r31, VCPU_GPR(R31)(r4)
197 stw r9, VCPU_FAULT_DEAR(r4)
203 stw r9, VCPU_FAULT_ESR(r4)
207 stw r0, VCPU_GPR(R0)(r4)
208 stw r1, VCPU_GPR(R1)(r4)
209 stw r2, VCPU_GPR(R2)(r4)
210 stw r10, VCPU_GPR(R10)(r4)
211 stw r11, VCPU_GPR(R11)(r4)
212 stw r12, VCPU_GPR(R12)(r4)
213 stw r13, VCPU_GPR(R13)(r4)
214 stw r14, VCPU_GPR(R14)(r4) /* We need a NV GPR below. */
216 stw r3, VCPU_LR(r4)
218 stw r3, VCPU_XER(r4)
222 lwz r1, VCPU_HOST_STACK(r4)
223 lwz r3, VCPU_HOST_PID(r4)
240 mr r3, r4
242 mr r14, r4 /* Save vcpu pointer. */
247 mr r4, r14
248 lwz r14, VCPU_GPR(R14)(r4)
253 lwz r15, VCPU_GPR(R15)(r4)
254 lwz r16, VCPU_GPR(R16)(r4)
255 lwz r17, VCPU_GPR(R17)(r4)
256 lwz r18, VCPU_GPR(R18)(r4)
257 lwz r19, VCPU_GPR(R19)(r4)
258 lwz r20, VCPU_GPR(R20)(r4)
259 lwz r21, VCPU_GPR(R21)(r4)
260 lwz r22, VCPU_GPR(R22)(r4)
261 lwz r23, VCPU_GPR(R23)(r4)
262 lwz r24, VCPU_GPR(R24)(r4)
263 lwz r25, VCPU_GPR(R25)(r4)
264 lwz r26, VCPU_GPR(R26)(r4)
265 lwz r27, VCPU_GPR(R27)(r4)
266 lwz r28, VCPU_GPR(R28)(r4)
267 lwz r29, VCPU_GPR(R29)(r4)
268 lwz r30, VCPU_GPR(R30)(r4)
269 lwz r31, VCPU_GPR(R31)(r4)
284 stw r9, VCPU_SPEFSCR(r4)
285 lwz r9, VCPU_HOST_SPEFSCR(r4)
291 stw r15, VCPU_GPR(R15)(r4)
292 stw r16, VCPU_GPR(R16)(r4)
293 stw r17, VCPU_GPR(R17)(r4)
294 stw r18, VCPU_GPR(R18)(r4)
295 stw r19, VCPU_GPR(R19)(r4)
296 stw r20, VCPU_GPR(R20)(r4)
297 stw r21, VCPU_GPR(R21)(r4)
298 stw r22, VCPU_GPR(R22)(r4)
299 stw r23, VCPU_GPR(R23)(r4)
300 stw r24, VCPU_GPR(R24)(r4)
301 stw r25, VCPU_GPR(R25)(r4)
302 stw r26, VCPU_GPR(R26)(r4)
303 stw r27, VCPU_GPR(R27)(r4)
304 stw r28, VCPU_GPR(R28)(r4)
305 stw r29, VCPU_GPR(R29)(r4)
306 stw r30, VCPU_GPR(R30)(r4)
307 stw r31, VCPU_GPR(R31)(r4)
330 lwz r4, HOST_STACK_LR(r1)
333 mtlr r4
347 mr r4, r3
374 lwz r14, VCPU_GPR(R14)(r4)
375 lwz r15, VCPU_GPR(R15)(r4)
376 lwz r16, VCPU_GPR(R16)(r4)
377 lwz r17, VCPU_GPR(R17)(r4)
378 lwz r18, VCPU_GPR(R18)(r4)
379 lwz r19, VCPU_GPR(R19)(r4)
380 lwz r20, VCPU_GPR(R20)(r4)
381 lwz r21, VCPU_GPR(R21)(r4)
382 lwz r22, VCPU_GPR(R22)(r4)
383 lwz r23, VCPU_GPR(R23)(r4)
384 lwz r24, VCPU_GPR(R24)(r4)
385 lwz r25, VCPU_GPR(R25)(r4)
386 lwz r26, VCPU_GPR(R26)(r4)
387 lwz r27, VCPU_GPR(R27)(r4)
388 lwz r28, VCPU_GPR(R28)(r4)
389 lwz r29, VCPU_GPR(R29)(r4)
390 lwz r30, VCPU_GPR(R30)(r4)
391 lwz r31, VCPU_GPR(R31)(r4)
396 stw r3, VCPU_HOST_SPEFSCR(r4)
397 lwz r3, VCPU_SPEFSCR(r4)
405 stw r3, VCPU_HOST_PID(r4)
406 lwz r3, VCPU_SHADOW_PID(r4)
410 lwz r3, VCPU_SHADOW_PID1(r4)
415 lwz r0, VCPU_GPR(R0)(r4)
416 lwz r2, VCPU_GPR(R2)(r4)
417 lwz r9, VCPU_GPR(R9)(r4)
418 lwz r10, VCPU_GPR(R10)(r4)
419 lwz r11, VCPU_GPR(R11)(r4)
420 lwz r12, VCPU_GPR(R12)(r4)
421 lwz r13, VCPU_GPR(R13)(r4)
422 lwz r3, VCPU_LR(r4)
424 lwz r3, VCPU_XER(r4)
433 lwz r5, VCPU_SHARED(r4)
437 lwz r1, VCPU_GPR(R1)(r4)
462 stw r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
463 stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
467 lwz r3, VCPU_CTR(r4)
468 lwz r5, VCPU_CR(r4)
469 lwz r6, VCPU_PC(r4)
470 lwz r7, VCPU_SHADOW_MSR(r4)
475 lwz r5, VCPU_GPR(R5)(r4)
476 lwz r6, VCPU_GPR(R6)(r4)
477 lwz r7, VCPU_GPR(R7)(r4)
478 lwz r8, VCPU_GPR(R8)(r4)
487 lwz r3, VCPU_GPR(R3)(r4)
488 lwz r4, VCPU_GPR(R4)(r4)
520 SAVE_32EVRS(0, r4, r3, VCPU_EVR)
523 li r4,VCPU_ACC
524 evstddx evr6, r4, r3 /* save acc */
530 li r4,VCPU_ACC
531 evlddx evr6,r4,r3
533 REST_32EVRS(0, r4, r3, VCPU_EVR)