Lines Matching refs:r10
109 stw r10,crit_r10@l(0) /* save two registers to work with */
111 mfspr r10,SPRN_SRR0
113 stw r10,crit_srr0@l(0)
115 mfspr r10,SPRN_DEAR
117 stw r10,crit_dear@l(0)
119 mfcr r10 /* save CR in r10 for now */
144 stw r10,_CCR(r11) /* save various registers */
147 mflr r10
148 stw r10,_LINK(r11)
150 lwz r10,crit_r10@l(r9)
152 stw r10,GPR10(r11)
275 mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */
282 mfspr r10, SPRN_DEAR /* Get faulting address */
288 cmplw r10, r11
307 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
312 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */
326 rlwimi r10, r9, 0, 20, 31
338 rlwimi r10, r9, 0, 20, 31
351 mfspr r10, SPRN_SPRG_SCRATCH5
359 mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */
366 mfspr r10, SPRN_SRR0 /* Get faulting address */
372 cmplw r10, r11
391 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
396 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */
410 rlwimi r10, r9, 0, 20, 31
422 rlwimi r10, r9, 0, 20, 31
435 mfspr r10, SPRN_SPRG_SCRATCH5
477 mfspr r10,SPRN_DBSR /* check single-step/branch taken */
478 andis. r10,r10,DBSR_IC@h
481 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */
484 mfspr r10,SPRN_SRR2 /* Faulting instruction address */
485 cmplwi r10,0x2100
490 lis r10,DBSR_IC@h /* clear the IC event */
491 mtspr SPRN_DBSR,r10
493 lwz r10,_CCR(r11)
496 mtcrf 0x80,r10
501 lwz r10,crit_r10@l(0)
575 tlbwe r10, r9, TLB_TAG /* Load TLB HI */
584 mfspr r10, SPRN_SPRG_SCRATCH5