Lines Matching refs:r4030_write_reg32
82 r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, in vdma_init()
84 r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE); in vdma_init()
85 r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0); in vdma_init()
153 r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0); in vdma_alloc()
309 r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5), in vdma_enable()
317 r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5), in vdma_enable()
348 r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5), in vdma_disable()
379 r4030_write_reg32(JAZZ_R4030_CHNL_MODE + (channel << 5), in vdma_set_mode()
388 r4030_write_reg32(JAZZ_R4030_CHNL_MODE + (channel << 5), in vdma_set_mode()
409 r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5), in vdma_set_mode()
416 r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5), in vdma_set_mode()
440 r4030_write_reg32(JAZZ_R4030_CHNL_ADDR + (channel << 5), addr); in vdma_set_addr()
454 r4030_write_reg32(JAZZ_R4030_CHNL_COUNT + (channel << 5), count); in vdma_set_count()