Lines Matching refs:BIT
171 #define QCA956X_MAC_CFG1_SOFT_RST BIT(31)
172 #define QCA956X_MAC_CFG1_RX_RST BIT(19)
173 #define QCA956X_MAC_CFG1_TX_RST BIT(18)
174 #define QCA956X_MAC_CFG1_LOOPBACK BIT(8)
175 #define QCA956X_MAC_CFG1_RX_EN BIT(2)
176 #define QCA956X_MAC_CFG1_TX_EN BIT(0)
179 #define QCA956X_MAC_CFG2_IF_1000 BIT(9)
180 #define QCA956X_MAC_CFG2_IF_10_100 BIT(8)
181 #define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5)
182 #define QCA956X_MAC_CFG2_LEN_CHECK BIT(4)
183 #define QCA956X_MAC_CFG2_PAD_CRC_EN BIT(2)
184 #define QCA956X_MAC_CFG2_FDX BIT(0)
198 #define QCA956X_INLINE_CHKSUM_ENG BIT(27)
266 #define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16)
267 #define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25)
305 #define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
337 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
338 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
339 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
346 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
347 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
348 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
350 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
377 #define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
378 #define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
379 #define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
386 #define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
387 #define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
388 #define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
415 #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
416 #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
417 #define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
424 #define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
425 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
426 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
428 #define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
429 #define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
430 #define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
465 #define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
466 #define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
467 #define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
474 #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
475 #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
476 #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
478 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5)
479 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6)
480 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7)
483 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP BIT(12)
484 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2 BIT(13)
485 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1 BIT(14)
486 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2 BIT(15)
487 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE BIT(16)
488 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE BIT(17)
489 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL BIT(18)
490 #define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL BIT(19)
492 #define QCA956X_PLL_ETH_XMII_TX_INVERT BIT(1)
493 #define QCA956X_PLL_ETH_XMII_GIGE BIT(25)
499 #define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
500 #define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
501 #define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
554 #define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
555 #define MISC_INT_ETHSW BIT(12)
556 #define MISC_INT_TIMER4 BIT(10)
557 #define MISC_INT_TIMER3 BIT(9)
558 #define MISC_INT_TIMER2 BIT(8)
559 #define MISC_INT_DMA BIT(7)
560 #define MISC_INT_OHCI BIT(6)
561 #define MISC_INT_PERFC BIT(5)
562 #define MISC_INT_WDOG BIT(4)
563 #define MISC_INT_UART BIT(3)
564 #define MISC_INT_GPIO BIT(2)
565 #define MISC_INT_ERROR BIT(1)
566 #define MISC_INT_TIMER BIT(0)
568 #define AR71XX_RESET_EXTERNAL BIT(28)
569 #define AR71XX_RESET_FULL_CHIP BIT(24)
570 #define AR71XX_RESET_CPU_NMI BIT(21)
571 #define AR71XX_RESET_CPU_COLD BIT(20)
572 #define AR71XX_RESET_DMA BIT(19)
573 #define AR71XX_RESET_SLIC BIT(18)
574 #define AR71XX_RESET_STEREO BIT(17)
575 #define AR71XX_RESET_DDR BIT(16)
576 #define AR71XX_RESET_GE1_MAC BIT(13)
577 #define AR71XX_RESET_GE1_PHY BIT(12)
578 #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
579 #define AR71XX_RESET_GE0_MAC BIT(9)
580 #define AR71XX_RESET_GE0_PHY BIT(8)
581 #define AR71XX_RESET_USB_OHCI_DLL BIT(6)
582 #define AR71XX_RESET_USB_HOST BIT(5)
583 #define AR71XX_RESET_USB_PHY BIT(4)
584 #define AR71XX_RESET_PCI_BUS BIT(1)
585 #define AR71XX_RESET_PCI_CORE BIT(0)
587 #define AR7240_RESET_USB_HOST BIT(5)
588 #define AR7240_RESET_OHCI_DLL BIT(3)
590 #define AR724X_RESET_GE1_MDIO BIT(23)
591 #define AR724X_RESET_GE0_MDIO BIT(22)
592 #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
593 #define AR724X_RESET_PCIE_PHY BIT(7)
594 #define AR724X_RESET_PCIE BIT(6)
595 #define AR724X_RESET_USB_HOST BIT(5)
596 #define AR724X_RESET_USB_PHY BIT(4)
597 #define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
599 #define AR913X_RESET_AMBA2WMAC BIT(22)
600 #define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
601 #define AR913X_RESET_USB_HOST BIT(5)
602 #define AR913X_RESET_USB_PHY BIT(4)
604 #define AR933X_RESET_GE1_MDIO BIT(23)
605 #define AR933X_RESET_GE0_MDIO BIT(22)
606 #define AR933X_RESET_GE1_MAC BIT(13)
607 #define AR933X_RESET_WMAC BIT(11)
608 #define AR933X_RESET_GE0_MAC BIT(9)
609 #define AR933X_RESET_USB_HOST BIT(5)
610 #define AR933X_RESET_USB_PHY BIT(4)
611 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
613 #define AR934X_RESET_HOST BIT(31)
614 #define AR934X_RESET_SLIC BIT(30)
615 #define AR934X_RESET_HDMA BIT(29)
616 #define AR934X_RESET_EXTERNAL BIT(28)
617 #define AR934X_RESET_RTC BIT(27)
618 #define AR934X_RESET_PCIE_EP_INT BIT(26)
619 #define AR934X_RESET_CHKSUM_ACC BIT(25)
620 #define AR934X_RESET_FULL_CHIP BIT(24)
621 #define AR934X_RESET_GE1_MDIO BIT(23)
622 #define AR934X_RESET_GE0_MDIO BIT(22)
623 #define AR934X_RESET_CPU_NMI BIT(21)
624 #define AR934X_RESET_CPU_COLD BIT(20)
625 #define AR934X_RESET_HOST_RESET_INT BIT(19)
626 #define AR934X_RESET_PCIE_EP BIT(18)
627 #define AR934X_RESET_UART1 BIT(17)
628 #define AR934X_RESET_DDR BIT(16)
629 #define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
630 #define AR934X_RESET_NANDF BIT(14)
631 #define AR934X_RESET_GE1_MAC BIT(13)
632 #define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
633 #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
634 #define AR934X_RESET_HOST_DMA_INT BIT(10)
635 #define AR934X_RESET_GE0_MAC BIT(9)
636 #define AR934X_RESET_ETH_SWITCH BIT(8)
637 #define AR934X_RESET_PCIE_PHY BIT(7)
638 #define AR934X_RESET_PCIE BIT(6)
639 #define AR934X_RESET_USB_HOST BIT(5)
640 #define AR934X_RESET_USB_PHY BIT(4)
641 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
642 #define AR934X_RESET_LUT BIT(2)
643 #define AR934X_RESET_MBOX BIT(1)
644 #define AR934X_RESET_I2S BIT(0)
646 #define QCA953X_RESET_USB_EXT_PWR BIT(29)
647 #define QCA953X_RESET_EXTERNAL BIT(28)
648 #define QCA953X_RESET_RTC BIT(27)
649 #define QCA953X_RESET_FULL_CHIP BIT(24)
650 #define QCA953X_RESET_GE1_MDIO BIT(23)
651 #define QCA953X_RESET_GE0_MDIO BIT(22)
652 #define QCA953X_RESET_CPU_NMI BIT(21)
653 #define QCA953X_RESET_CPU_COLD BIT(20)
654 #define QCA953X_RESET_DDR BIT(16)
655 #define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
656 #define QCA953X_RESET_GE1_MAC BIT(13)
657 #define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
658 #define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
659 #define QCA953X_RESET_GE0_MAC BIT(9)
660 #define QCA953X_RESET_ETH_SWITCH BIT(8)
661 #define QCA953X_RESET_PCIE_PHY BIT(7)
662 #define QCA953X_RESET_PCIE BIT(6)
663 #define QCA953X_RESET_USB_HOST BIT(5)
664 #define QCA953X_RESET_USB_PHY BIT(4)
665 #define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
667 #define QCA955X_RESET_HOST BIT(31)
668 #define QCA955X_RESET_SLIC BIT(30)
669 #define QCA955X_RESET_HDMA BIT(29)
670 #define QCA955X_RESET_EXTERNAL BIT(28)
671 #define QCA955X_RESET_RTC BIT(27)
672 #define QCA955X_RESET_PCIE_EP_INT BIT(26)
673 #define QCA955X_RESET_CHKSUM_ACC BIT(25)
674 #define QCA955X_RESET_FULL_CHIP BIT(24)
675 #define QCA955X_RESET_GE1_MDIO BIT(23)
676 #define QCA955X_RESET_GE0_MDIO BIT(22)
677 #define QCA955X_RESET_CPU_NMI BIT(21)
678 #define QCA955X_RESET_CPU_COLD BIT(20)
679 #define QCA955X_RESET_HOST_RESET_INT BIT(19)
680 #define QCA955X_RESET_PCIE_EP BIT(18)
681 #define QCA955X_RESET_UART1 BIT(17)
682 #define QCA955X_RESET_DDR BIT(16)
683 #define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
684 #define QCA955X_RESET_NANDF BIT(14)
685 #define QCA955X_RESET_GE1_MAC BIT(13)
686 #define QCA955X_RESET_SGMII_ANALOG BIT(12)
687 #define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
688 #define QCA955X_RESET_HOST_DMA_INT BIT(10)
689 #define QCA955X_RESET_GE0_MAC BIT(9)
690 #define QCA955X_RESET_SGMII BIT(8)
691 #define QCA955X_RESET_PCIE_PHY BIT(7)
692 #define QCA955X_RESET_PCIE BIT(6)
693 #define QCA955X_RESET_USB_HOST BIT(5)
694 #define QCA955X_RESET_USB_PHY BIT(4)
695 #define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
696 #define QCA955X_RESET_LUT BIT(2)
697 #define QCA955X_RESET_MBOX BIT(1)
698 #define QCA955X_RESET_I2S BIT(0)
700 #define QCA956X_RESET_EXTERNAL BIT(28)
701 #define QCA956X_RESET_FULL_CHIP BIT(24)
702 #define QCA956X_RESET_GE1_MDIO BIT(23)
703 #define QCA956X_RESET_GE0_MDIO BIT(22)
704 #define QCA956X_RESET_CPU_NMI BIT(21)
705 #define QCA956X_RESET_CPU_COLD BIT(20)
706 #define QCA956X_RESET_DMA BIT(19)
707 #define QCA956X_RESET_DDR BIT(16)
708 #define QCA956X_RESET_GE1_MAC BIT(13)
709 #define QCA956X_RESET_SGMII_ANALOG BIT(12)
710 #define QCA956X_RESET_USB_PHY_ANALOG BIT(11)
711 #define QCA956X_RESET_GE0_MAC BIT(9)
712 #define QCA956X_RESET_SGMII BIT(8)
713 #define QCA956X_RESET_USB_HOST BIT(5)
714 #define QCA956X_RESET_USB_PHY BIT(4)
715 #define QCA956X_RESET_USBSUS_OVERRIDE BIT(3)
716 #define QCA956X_RESET_SWITCH_ANALOG BIT(2)
717 #define QCA956X_RESET_SWITCH BIT(0)
719 #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
720 #define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
721 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
723 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
724 #define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
725 #define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
726 #define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
727 #define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
728 #define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
729 #define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
730 #define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
731 #define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
732 #define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
733 #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
734 #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
735 #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
736 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
737 #define AR934X_BOOTSTRAP_DDR1 BIT(0)
739 #define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
740 #define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
741 #define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
742 #define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
743 #define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
744 #define QCA953X_BOOTSTRAP_DDR1 BIT(0)
746 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
748 #define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
750 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
751 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
752 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
753 #define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
754 #define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
755 #define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
756 #define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
757 #define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
758 #define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
768 #define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
769 #define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
770 #define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
771 #define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
772 #define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
773 #define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
774 #define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
775 #define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
776 #define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
786 #define QCA955X_EXT_INT_WMAC_MISC BIT(0)
787 #define QCA955X_EXT_INT_WMAC_TX BIT(1)
788 #define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
789 #define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
790 #define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
791 #define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
792 #define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
793 #define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
794 #define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
795 #define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
796 #define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
797 #define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
798 #define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
799 #define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
800 #define QCA955X_EXT_INT_USB1 BIT(24)
801 #define QCA955X_EXT_INT_USB2 BIT(28)
817 #define QCA956X_EXT_INT_WMAC_MISC BIT(0)
818 #define QCA956X_EXT_INT_WMAC_TX BIT(1)
819 #define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
820 #define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
821 #define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
822 #define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
823 #define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
824 #define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
825 #define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
826 #define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
827 #define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
828 #define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
829 #define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
830 #define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
831 #define QCA956X_EXT_INT_USB1 BIT(24)
832 #define QCA956X_EXT_INT_USB2 BIT(28)
900 #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
902 #define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */
905 #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
906 #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
907 #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
1004 #define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
1022 #define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
1026 #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
1027 #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
1028 #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
1029 #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
1030 #define AR71XX_GPIO_FUNC_UART_EN BIT(8)
1031 #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
1032 #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
1034 #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
1035 #define AR724X_GPIO_FUNC_SPI_EN BIT(18)
1036 #define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
1037 #define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
1038 #define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
1039 #define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
1040 #define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
1041 #define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
1042 #define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
1043 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
1044 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
1045 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
1046 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
1047 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
1048 #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
1049 #define AR724X_GPIO_FUNC_UART_EN BIT(1)
1050 #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
1052 #define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
1053 #define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
1054 #define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
1055 #define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
1056 #define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
1057 #define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
1058 #define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
1059 #define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
1060 #define AR913X_GPIO_FUNC_UART_EN BIT(8)
1061 #define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
1063 #define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
1064 #define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
1065 #define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
1066 #define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
1067 #define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
1068 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
1069 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
1070 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
1071 #define AR933X_GPIO_FUNC_SPI_EN BIT(18)
1072 #define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
1073 #define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
1074 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
1075 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
1076 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
1077 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
1078 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
1079 #define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
1080 #define AR933X_GPIO_FUNC_UART_EN BIT(1)
1081 #define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
1083 #define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
1084 #define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
1085 #define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
1086 #define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
1087 #define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
1088 #define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
1089 #define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
1090 #define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
1091 #define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
1103 #define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
1104 #define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
1105 #define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
1106 #define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
1107 #define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
1108 #define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
1109 #define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
1110 #define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1)
1194 #define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
1195 #define AR933X_ETH_CFG_MII_GE0 BIT(1)
1196 #define AR933X_ETH_CFG_GMII_GE0 BIT(2)
1197 #define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
1198 #define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
1199 #define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
1200 #define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
1201 #define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
1202 #define AR933X_ETH_CFG_RMII_GE0 BIT(9)
1204 #define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
1211 #define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
1212 #define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
1213 #define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
1214 #define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
1215 #define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
1216 #define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
1217 #define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
1218 #define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
1219 #define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
1220 #define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
1221 #define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
1222 #define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
1223 #define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
1224 #define AR934X_ETH_CFG_RXD_DELAY BIT(14)
1227 #define AR934X_ETH_CFG_RDV_DELAY BIT(16)
1236 #define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
1237 #define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
1238 #define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
1239 #define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
1248 #define QCA955X_ETH_CFG_RGMII_EN BIT(0)
1249 #define QCA955X_ETH_CFG_MII_GE0 BIT(1)
1250 #define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
1251 #define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
1252 #define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
1253 #define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
1254 #define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
1255 #define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
1256 #define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
1257 #define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
1260 #define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
1268 #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
1282 #define QCA956X_ETH_CFG_RGMII_EN BIT(0)
1283 #define QCA956X_ETH_CFG_GE0_SGMII BIT(6)
1284 #define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7)
1285 #define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8)
1286 #define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9)
1287 #define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10)
1288 #define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
1295 #define QCA956X_SGMII_RESET_RX_CLK_N BIT(0)
1296 #define QCA956X_SGMII_RESET_TX_CLK_N BIT(1)
1297 #define QCA956X_SGMII_RESET_RX_125M_N BIT(2)
1298 #define QCA956X_SGMII_RESET_TX_125M_N BIT(3)
1299 #define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4)
1305 #define QCA956X_SGMII_SERDES_PLL_BW BIT(8)
1306 #define QCA956X_SGMII_SERDES_VCO_FAST BIT(9)
1307 #define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10)
1308 #define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
1309 #define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16)
1310 #define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17)
1316 #define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12)
1317 #define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15)