293 	__raw_writel(1 << bit, base + IC_MASKSET);  in au1x_ic0_unmask()
294 	__raw_writel(1 << bit, base + IC_WAKESET);  in au1x_ic0_unmask()
303 	__raw_writel(1 << bit, base + IC_MASKSET);  in au1x_ic1_unmask()
304 	__raw_writel(1 << bit, base + IC_WAKESET);  in au1x_ic1_unmask()
313 	__raw_writel(1 << bit, base + IC_MASKCLR);  in au1x_ic0_mask()
314 	__raw_writel(1 << bit, base + IC_WAKECLR);  in au1x_ic0_mask()
323 	__raw_writel(1 << bit, base + IC_MASKCLR);  in au1x_ic1_mask()
324 	__raw_writel(1 << bit, base + IC_WAKECLR);  in au1x_ic1_mask()
337 	__raw_writel(1 << bit, base + IC_FALLINGCLR);  in au1x_ic0_ack()
338 	__raw_writel(1 << bit, base + IC_RISINGCLR);  in au1x_ic0_ack()
351 	__raw_writel(1 << bit, base + IC_FALLINGCLR);  in au1x_ic1_ack()
352 	__raw_writel(1 << bit, base + IC_RISINGCLR);  in au1x_ic1_ack()
361 	__raw_writel(1 << bit, base + IC_WAKECLR);  in au1x_ic0_maskack()
362 	__raw_writel(1 << bit, base + IC_MASKCLR);  in au1x_ic0_maskack()
363 	__raw_writel(1 << bit, base + IC_RISINGCLR);  in au1x_ic0_maskack()
364 	__raw_writel(1 << bit, base + IC_FALLINGCLR);  in au1x_ic0_maskack()
373 	__raw_writel(1 << bit, base + IC_WAKECLR);  in au1x_ic1_maskack()
374 	__raw_writel(1 << bit, base + IC_MASKCLR);  in au1x_ic1_maskack()
375 	__raw_writel(1 << bit, base + IC_RISINGCLR);  in au1x_ic1_maskack()
376 	__raw_writel(1 << bit, base + IC_FALLINGCLR);  in au1x_ic1_maskack()
452 		__raw_writel(1 << bit, base + IC_CFG2CLR);  in au1x_ic_settype()
453 		__raw_writel(1 << bit, base + IC_CFG1CLR);  in au1x_ic_settype()
454 		__raw_writel(1 << bit, base + IC_CFG0SET);  in au1x_ic_settype()
459 		__raw_writel(1 << bit, base + IC_CFG2CLR);  in au1x_ic_settype()
460 		__raw_writel(1 << bit, base + IC_CFG1SET);  in au1x_ic_settype()
461 		__raw_writel(1 << bit, base + IC_CFG0CLR);  in au1x_ic_settype()
466 		__raw_writel(1 << bit, base + IC_CFG2CLR);  in au1x_ic_settype()
467 		__raw_writel(1 << bit, base + IC_CFG1SET);  in au1x_ic_settype()
468 		__raw_writel(1 << bit, base + IC_CFG0SET);  in au1x_ic_settype()
473 		__raw_writel(1 << bit, base + IC_CFG2SET);  in au1x_ic_settype()
474 		__raw_writel(1 << bit, base + IC_CFG1CLR);  in au1x_ic_settype()
475 		__raw_writel(1 << bit, base + IC_CFG0SET);  in au1x_ic_settype()
480 		__raw_writel(1 << bit, base + IC_CFG2SET);  in au1x_ic_settype()
481 		__raw_writel(1 << bit, base + IC_CFG1SET);  in au1x_ic_settype()
482 		__raw_writel(1 << bit, base + IC_CFG0CLR);  in au1x_ic_settype()
487 		__raw_writel(1 << bit, base + IC_CFG2CLR);  in au1x_ic_settype()
488 		__raw_writel(1 << bit, base + IC_CFG1CLR);  in au1x_ic_settype()
489 		__raw_writel(1 << bit, base + IC_CFG0CLR);  in au1x_ic_settype()
523 	__raw_writel(l, r + AU1300_GPIC_PINCFG);  in au1300_gpic_chgcfg()
556 	__raw_writel(bit, r + AU1300_GPIC_DEVSEL);  in au1300_pinfunc_to_dev()
589 		__raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);  in au1300_set_dbdma_gpio()
608 	__raw_writel(bit, r + AU1300_GPIC_IDIS);  in au1300_gpic_mask()
625 	__raw_writel(bit, r + AU1300_GPIC_IEN);  in au1300_gpic_unmask()
637 	__raw_writel(bit, r + AU1300_GPIC_IPEND);	/* ack */  in au1300_gpic_maskack()
638 	__raw_writel(bit, r + AU1300_GPIC_IDIS);	/* mask */  in au1300_gpic_maskack()
652 	__raw_writel(bit, r + AU1300_GPIC_IPEND);	/* ack */  in au1300_gpic_ack()
718 	__raw_writel(0xffffffff, base + IC_CFG0CLR);  in ic_init()
719 	__raw_writel(0xffffffff, base + IC_CFG1CLR);  in ic_init()
720 	__raw_writel(0xffffffff, base + IC_CFG2CLR);  in ic_init()
721 	__raw_writel(0xffffffff, base + IC_MASKCLR);  in ic_init()
722 	__raw_writel(0xffffffff, base + IC_ASSIGNCLR);  in ic_init()
723 	__raw_writel(0xffffffff, base + IC_WAKECLR);  in ic_init()
724 	__raw_writel(0xffffffff, base + IC_SRCSET);  in ic_init()
725 	__raw_writel(0xffffffff, base + IC_FALLINGCLR);  in ic_init()
726 	__raw_writel(0xffffffff, base + IC_RISINGCLR);  in ic_init()
727 	__raw_writel(0x00000000, base + IC_TESTBIT);  in ic_init()
749 	__raw_writel(d[0], base + IC_CFG0SET);  in alchemy_ic_resume_one()
750 	__raw_writel(d[1], base + IC_CFG1SET);  in alchemy_ic_resume_one()
751 	__raw_writel(d[2], base + IC_CFG2SET);  in alchemy_ic_resume_one()
752 	__raw_writel(d[3], base + IC_SRCSET);  in alchemy_ic_resume_one()
753 	__raw_writel(d[4], base + IC_ASSIGNSET);  in alchemy_ic_resume_one()
754 	__raw_writel(d[5], base + IC_WAKESET);  in alchemy_ic_resume_one()
757 	__raw_writel(d[6], base + IC_MASKSET);  in alchemy_ic_resume_one()
793 	__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);  in alchemy_gpic_suspend()
794 	__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);  in alchemy_gpic_suspend()
795 	__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);  in alchemy_gpic_suspend()
796 	__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);  in alchemy_gpic_suspend()
815 	__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);  in alchemy_gpic_resume()
816 	__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);  in alchemy_gpic_resume()
817 	__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);  in alchemy_gpic_resume()
818 	__raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);  in alchemy_gpic_resume()
824 		__raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2));  in alchemy_gpic_resume()
829 	__raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL);  in alchemy_gpic_resume()
833 	__raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0);  in alchemy_gpic_resume()
834 	__raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4);  in alchemy_gpic_resume()
835 	__raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8);  in alchemy_gpic_resume()
836 	__raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc);  in alchemy_gpic_resume()
911 			__raw_writel(1 << bit, base + IC_ASSIGNSET);  in au1000_init_irq()
934 		__raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS);  in alchemy_gpic_init_irq()
936 		__raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND);  in alchemy_gpic_init_irq()