Lines Matching refs:MCF_MBAR
27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
29 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
30 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
31 #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
32 #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */
34 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
35 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
36 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
37 #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
38 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
39 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
40 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
41 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
42 #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
43 #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
44 #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
45 #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
46 #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
47 #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
48 #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
49 #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
58 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
59 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
60 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
61 #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
62 #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
63 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
64 #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
65 #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
66 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
67 #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
68 #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
69 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
70 #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
71 #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
72 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
73 #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
74 #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
75 #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
77 #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
78 #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
79 #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
80 #define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
81 #define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
86 #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
87 #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
89 #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
90 #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
92 #define MCFSIM_PADDR (MCF_MBAR + 0x244)
93 #define MCFSIM_PADAT (MCF_MBAR + 0x248)
98 #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
99 #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
100 #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
101 #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
151 #define MCFI2C_BASE0 (MCF_MBAR + 0x280)