Lines Matching refs:r18
68 ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));; // r18=ptce_base
85 ptc.e r18
87 add r18=r22,r18
90 add r18=r21,r18
101 mov r18=KERNEL_TR_PAGE_SHIFT<<2
103 ptr.i r16, r18
104 ptr.d r16, r18
114 mov r18=IA64_GRANULE_SHIFT<<2
116 ptr.i r16,r18
127 mov r18=IA64_GRANULE_SHIFT<<2
129 ptr.d r16,r18
153 ld8 r18=[r3] // Get processor state parameter on existing PALE_CHECK.
155 tbit.nz p6,p7=r18,60
161 movl r18=ia64_reload_tr;;
162 LOAD_PHYSICAL(p0,r18,ia64_reload_tr);;
163 mov b1=r18;;
169 mov r18=KERNEL_TR_PAGE_SHIFT<<2
172 mov cr.itir=r18
176 movl r18=PAGE_KERNEL
180 or r18=r17,r18
182 itr.i itr[r16]=r18
184 itr.d dtr[r16]=r18
192 ld8 r18=[r2] // load PAL PTE
203 itr.i itr[r20]=r18
213 add r18=r19,r16
220 mov cr.ifa=r18
225 mov r18 = 1
229 st8 [r2] =r18
475 st8 [temp1]=r18 // proc_state_param
869 mov r18=IA64_GRANULE_SHIFT<<2 // for cr.itir.ps
871 ptr.d r15,r18
884 mov cr.itir=r18
1044 mov r18=IA64_GRANULE_SHIFT<<2 // for cr.itir.ps
1046 ptr.d r16,r18
1056 mov cr.itir=r18