Lines Matching refs:cmcv
639 cmcv_reg_t cmcv; in ia64_mca_cmc_vector_setup() local
641 cmcv.cmcv_regval = 0; in ia64_mca_cmc_vector_setup()
642 cmcv.cmcv_mask = 1; /* Mask/disable interrupt at first */ in ia64_mca_cmc_vector_setup()
643 cmcv.cmcv_vector = IA64_CMC_VECTOR; in ia64_mca_cmc_vector_setup()
644 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); in ia64_mca_cmc_vector_setup()
668 cmcv_reg_t cmcv; in ia64_mca_cmc_vector_disable() local
670 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV); in ia64_mca_cmc_vector_disable()
672 cmcv.cmcv_mask = 1; /* Mask/disable interrupt */ in ia64_mca_cmc_vector_disable()
673 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); in ia64_mca_cmc_vector_disable()
676 __func__, smp_processor_id(), cmcv.cmcv_vector); in ia64_mca_cmc_vector_disable()
694 cmcv_reg_t cmcv; in ia64_mca_cmc_vector_enable() local
696 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV); in ia64_mca_cmc_vector_enable()
698 cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */ in ia64_mca_cmc_vector_enable()
699 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); in ia64_mca_cmc_vector_enable()
702 __func__, smp_processor_id(), cmcv.cmcv_vector); in ia64_mca_cmc_vector_enable()