Lines Matching refs:r17
124 shr.u r17=r16,61 // get the region number into r17
137 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
140 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
149 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
150 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
158 ld8 r17=[r17] // get *pgd (may be 0)
160 (p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?
162 dep r28=r28,r17,3,(PAGE_SHIFT-3) // r28=pud_offset(pgd,addr)
168 dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
170 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr)
173 (p7) ld8 r20=[r17] // get *pmd (may be 0)
227 ld8 r26=[r17] // read *pmd again
264 MOV_FROM_IHA(r17) // get virtual address of PTE
267 1: ld8 r18=[r17] // read *pte
282 ld8 r19=[r17] // read *pte again and see if same
308 MOV_FROM_IHA(r17) // get virtual address of PTE
311 1: ld8 r18=[r17] // read *pte
326 ld8 r19=[r17] // read *pte again and see if same
343 movl r17=PAGE_KERNEL
353 THASH(p8, r17, r16, r23)
355 MOV_TO_IHA(p8, r17, r23)
365 or r19=r17,r19 // insert PTE control bits into r19
381 movl r17=PAGE_KERNEL
393 THASH(p8, r17, r16, r25)
395 MOV_TO_IHA(p8, r17, r25)
417 (p12) dep r17=-1,r17,4,1 // set ma=UC for region 6 addr
422 or r19=r19,r17 // insert PTE control bits into r19
461 shr.u r17=r16,61 // get the region number into r17
464 cmp.eq p6,p7=5,r17 // is faulting address in region 5?
470 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
479 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
480 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
488 ld8 r17=[r17] // get *pgd (may be 0)
490 (p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?
491 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=p[u|m]d_offset(pgd,addr)
494 (p7) ld8 r17=[r17] // get *pud (may be 0)
497 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pud_present(*pud) == NULL?
498 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
501 (p7) ld8 r17=[r17] // get *pmd (may be 0)
504 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pmd_present(*pmd) == NULL?
505 dep r17=r19,r17,3,(PAGE_SHIFT-3) // r17=pte_offset(pmd,addr);
544 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
550 1: ld8 r18=[r17]
556 (p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only update if page is present
569 ld8 r18=[r17] // read PTE again
578 1: ld8 r18=[r17]
583 st8 [r17]=r18 // store back updated PTE
603 MOV_FROM_IPSR(p0, r17)
606 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set?
611 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
616 1: ld8 r18=[r17]
622 (p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only if page present
635 ld8 r18=[r17] // read PTE again
644 1: ld8 r18=[r17]
649 st8 [r17]=r18 // store back updated PTE
665 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
671 1: ld8 r18=[r17]
677 (p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only if page is present
689 ld8 r18=[r17] // read PTE again
697 1: ld8 r18=[r17]
701 st8 [r17]=r18 // store back updated PTE
733 MOV_FROM_IIM(r17) // M2 (2 cyc)
753 cmp.eq p0,p7=r18,r17 // I0 is this a system call?
768 ld1.bias r17=[r16] // M0|1 r17 = current->thread.on_ustack flag
812 cmp.eq pKStk,pUStk=r0,r17 // A were we on kernel stacks already?
826 add r17=TI_AC_LEAVE+IA64_TASK_SIZE,r13 // A
830 ld8 r19=[r17],TI_AC_UTIME-TI_AC_LEAVE // M time at leave
833 ld8 r21=[r17] // M cumulated utime
843 st8 [r17]=r21 // M update utime
949 add r17=PT(R11),r1 // initialize second base pointer
955 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
961 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip
965 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat
974 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
984 (pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field
992 (pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore
996 st8 [r17]=r28,PT(R1)-PT(B0) // save b0
1000 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
1005 .mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
1016 st8.spill [r17]=r15 // save r15
1028 movl r17=FPSR_DEFAULT
1030 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
1060 add r17=TI_AC_LEAVE+IA64_TASK_SIZE,r13
1063 ld8 r19=[r17],TI_AC_UTIME-TI_AC_LEAVE // time at left from kernel
1066 ld8 r21=[r17] // cumulated utime
1076 st8 [r17]=r21 // update utime
1115 mov r17=PAGE_SHIFT<<2
1117 ptc.l r16,r17
1198 MOV_FROM_ISR(r17)
1201 and r18=0xf,r17 // r18 = cr.ipsr.code{3:0}
1202 tbit.z p6,p0=r17,IA64_ISR_NA_BIT
1235 MOV_FROM_IIP(r17)
1243 add r17=r17,r18 // now add the offset
1245 MOV_TO_IIP(r17, r19)