Lines Matching refs:tmp2
454 .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
455 dcache_line_size \tmp1, \tmp2
456 dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup
467 .macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup
468 icache_line_size \tmp1, \tmp2
469 sub \tmp2, \tmp1, #1
470 bic \tmp2, \start, \tmp2
472 ic ivau, \tmp2 // invalidate I line PoU
473 add \tmp2, \tmp2, \tmp1
474 cmp \tmp2, \end
487 .macro load_ttbr1, pgtbl, tmp1, tmp2
489 offset_ttbr1 \tmp1, \tmp2
501 .macro break_before_make_ttbr_switch zero_page, page_table, tmp, tmp2
507 load_ttbr1 \page_table, \tmp, \tmp2
675 .macro tcr_clear_errata_bits, tcr, tmp1, tmp2
679 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK
680 and \tmp1, \tmp1, \tmp2
681 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001
682 cmp \tmp1, \tmp2
685 mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001
686 bic \tcr, \tcr, \tmp2
798 .macro cond_yield, lbl:req, tmp:req, tmp2:req
812 get_this_cpu_offset \tmp2
813 ldr w\tmp, [\tmp, \tmp2]