Lines Matching refs:W3
72 #define W3 v3 macro
195 ld1 {W3.16b}, [RDATA], #16;
203 rev32 XTMP3.16b, W3.16b;
225 ext W3.16b, XTMP1.16b, XTMP2.16b, #12; /* W3: xx, w9, w8, w7 */
305 SCHED_W_1_##iop_num(round, W0, W1, W2, W3, W4, W5)
307 SCHED_W_2_##iop_num(round, W0, W1, W2, W3, W4, W5)
309 SCHED_W_3_##iop_num(round, W0, W1, W2, W3, W4, W5)
312 SCHED_W_1_##iop_num(round, W1, W2, W3, W4, W5, W0)
314 SCHED_W_2_##iop_num(round, W1, W2, W3, W4, W5, W0)
316 SCHED_W_3_##iop_num(round, W1, W2, W3, W4, W5, W0)
319 SCHED_W_1_##iop_num(round, W2, W3, W4, W5, W0, W1)
321 SCHED_W_2_##iop_num(round, W2, W3, W4, W5, W0, W1)
323 SCHED_W_3_##iop_num(round, W2, W3, W4, W5, W0, W1)
326 SCHED_W_1_##iop_num(round, W3, W4, W5, W0, W1, W2)
328 SCHED_W_2_##iop_num(round, W3, W4, W5, W0, W1, W2)
330 SCHED_W_3_##iop_num(round, W3, W4, W5, W0, W1, W2)
333 SCHED_W_1_##iop_num(round, W4, W5, W0, W1, W2, W3)
335 SCHED_W_2_##iop_num(round, W4, W5, W0, W1, W2, W3)
337 SCHED_W_3_##iop_num(round, W4, W5, W0, W1, W2, W3)
340 SCHED_W_1_##iop_num(round, W5, W0, W1, W2, W3, W4)
342 SCHED_W_2_##iop_num(round, W5, W0, W1, W2, W3, W4)
344 SCHED_W_3_##iop_num(round, W5, W0, W1, W2, W3, W4)
543 clear_vec(W3)
566 st1 {W0.16b-W3.16b}, [addr0], #64
567 st1 {W0.16b-W3.16b}, [addr0], #64
568 st1 {W0.16b-W3.16b}, [addr0]