Lines Matching refs:cpg
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
180 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
181 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
184 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
187 power-domains = <&cpg>;
201 clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
202 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
205 resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
208 power-domains = <&cpg>;
222 clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
223 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
226 resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
229 power-domains = <&cpg>;
243 clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
244 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
247 resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
250 power-domains = <&cpg>;
262 clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
263 resets = <&cpg R9A07G054_RSPI0_RST>;
266 power-domains = <&cpg>;
280 clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
281 resets = <&cpg R9A07G054_RSPI1_RST>;
284 power-domains = <&cpg>;
298 clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
299 resets = <&cpg R9A07G054_RSPI2_RST>;
302 power-domains = <&cpg>;
321 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
323 power-domains = <&cpg>;
324 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
340 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
342 power-domains = <&cpg>;
343 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
359 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
361 power-domains = <&cpg>;
362 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
378 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
380 power-domains = <&cpg>;
381 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
397 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
399 power-domains = <&cpg>;
400 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
412 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
414 power-domains = <&cpg>;
415 resets = <&cpg R9A07G054_SCI0_RST>;
427 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
429 power-domains = <&cpg>;
430 resets = <&cpg R9A07G054_SCI1_RST>;
448 clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
449 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
452 assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
454 resets = <&cpg R9A07G054_CANFD_RSTP_N>,
455 <&cpg R9A07G054_CANFD_RSTC_N>;
457 power-domains = <&cpg>;
483 clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
485 resets = <&cpg R9A07G054_I2C0_MRST>;
486 power-domains = <&cpg>;
505 clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
507 resets = <&cpg R9A07G054_I2C1_MRST>;
508 power-domains = <&cpg>;
527 clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
529 resets = <&cpg R9A07G054_I2C2_MRST>;
530 power-domains = <&cpg>;
549 clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
551 resets = <&cpg R9A07G054_I2C3_MRST>;
552 power-domains = <&cpg>;
560 clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
561 <&cpg CPG_MOD R9A07G054_ADC_PCLK>;
563 resets = <&cpg R9A07G054_ADC_PRESETN>,
564 <&cpg R9A07G054_ADC_ADRST_N>;
566 power-domains = <&cpg>;
602 clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
603 resets = <&cpg R9A07G054_TSU_PRESETN>;
604 power-domains = <&cpg>;
616 clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
617 <&cpg CPG_MOD R9A07G054_SPI_CLK>;
618 resets = <&cpg R9A07G054_SPI_RST>;
619 power-domains = <&cpg>;
625 cpg: clock-controller@11010000 { label
626 compatible = "renesas,r9a07g054-cpg";
658 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
659 power-domains = <&cpg>;
660 resets = <&cpg R9A07G054_GPIO_RSTN>,
661 <&cpg R9A07G054_GPIO_PORT_RESETN>,
662 <&cpg R9A07G054_GPIO_SPARE_RESETN>;
713 clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
714 <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
716 power-domains = <&cpg>;
717 resets = <&cpg R9A07G054_IA55_RESETN>;
747 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
748 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
749 power-domains = <&cpg>;
750 resets = <&cpg R9A07G054_DMAC_ARESETN>,
751 <&cpg R9A07G054_DMAC_RST_ASYNC>;
765 clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
766 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
767 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
769 power-domains = <&cpg>;
770 resets = <&cpg R9A07G054_GPU_RESETN>,
771 <&cpg R9A07G054_GPU_AXI_RESETN>,
772 <&cpg R9A07G054_GPU_ACE_RESETN>;
793 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
794 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
795 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
796 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
798 resets = <&cpg R9A07G054_SDHI0_IXRST>;
799 power-domains = <&cpg>;
809 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
810 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
811 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
812 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
814 resets = <&cpg R9A07G054_SDHI1_IXRST>;
815 power-domains = <&cpg>;
828 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
829 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
830 <&cpg CPG_CORE R9A07G054_CLK_HP>;
832 resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
833 power-domains = <&cpg>;
848 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
849 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
850 <&cpg CPG_CORE R9A07G054_CLK_HP>;
852 resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
853 power-domains = <&cpg>;
863 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
864 resets = <&cpg R9A07G054_USB_PRESETN>;
865 power-domains = <&cpg>;
874 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
875 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
877 <&cpg R9A07G054_USB_U2H0_HRESETN>;
880 power-domains = <&cpg>;
888 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
889 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
891 <&cpg R9A07G054_USB_U2H1_HRESETN>;
894 power-domains = <&cpg>;
902 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
903 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
905 <&cpg R9A07G054_USB_U2H0_HRESETN>;
909 power-domains = <&cpg>;
917 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
918 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
920 <&cpg R9A07G054_USB_U2H1_HRESETN>;
924 power-domains = <&cpg>;
933 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
934 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
937 power-domains = <&cpg>;
946 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
947 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
950 power-domains = <&cpg>;
962 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
963 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
965 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
969 power-domains = <&cpg>;
977 clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
978 <&cpg CPG_MOD R9A07G054_WDT0_CLK>;
983 resets = <&cpg R9A07G054_WDT0_PRESETN>;
984 power-domains = <&cpg>;
992 clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
993 <&cpg CPG_MOD R9A07G054_WDT1_CLK>;
998 resets = <&cpg R9A07G054_WDT1_PRESETN>;
999 power-domains = <&cpg>;
1007 clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>,
1008 <&cpg CPG_MOD R9A07G054_WDT2_CLK>;
1013 resets = <&cpg R9A07G054_WDT2_PRESETN>;
1014 power-domains = <&cpg>;
1023 clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
1024 resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
1025 power-domains = <&cpg>;
1034 clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
1035 resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
1036 power-domains = <&cpg>;
1045 clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
1046 resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
1047 power-domains = <&cpg>;