Lines Matching refs:mmsys
393 <&mmsys CLK_MM_SMI_INFRA>,
394 <&mmsys CLK_MM_SMI_COMMON>,
395 <&mmsys CLK_MM_SMI_GALS>,
396 <&mmsys CLK_MM_SMI_IOMMU>;
1207 mmsys: syscon@14000000 { label
1208 compatible = "mediatek,mt8192-mmsys", "syscon";
1221 clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1230 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1231 <&mmsys CLK_MM_SMI_INFRA>,
1232 <&mmsys CLK_MM_SMI_GALS>,
1233 <&mmsys CLK_MM_SMI_GALS>;
1262 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1274 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1285 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1298 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1307 clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1317 clocks = <&mmsys CLK_MM_DISP_AAL0>;
1327 clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1336 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
1346 clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1354 clocks = <&mmsys CLK_MM_DSI0>,
1355 <&mmsys CLK_MM_DSI_DSI0>,
1361 resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
1374 clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
1386 clocks = <&mmsys CLK_MM_DISP_RDMA4>;
1396 clocks = <&mmsys CLK_MM_DPI_DPI0>,
1397 <&mmsys CLK_MM_DISP_DPI0>,
1412 clocks = <&mmsys CLK_MM_SMI_IOMMU>;