Lines Matching refs:p15
56 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
89 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
174 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
175 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
202 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
203 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
204 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
224 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
230 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
231 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
245 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
250 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
251 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
252 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
269 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
271 mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
272 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
276 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
289 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
293 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
306 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
310 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
344 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
362 mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
363 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
364 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
366 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
367 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
417 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
418 mrc p15, 0, r6, c13, c0, 0 @ PID
419 mrc p15, 0, r7, c3, c0, 0 @ domain ID
420 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
421 mrc p15, 0, r9, c1, c0, 0 @ control reg
430 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
431 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
432 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
433 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
435 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
436 mcr p15, 0, r6, c13, c0, 0 @ PID
437 mcr p15, 0, r7, c3, c0, 0 @ domain ID
439 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
440 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
450 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
451 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
452 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
453 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
455 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
458 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
460 mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
463 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
469 mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
474 mrc p15, 0, r0, c1, c0, 0 @ get control register