Lines Matching refs:mcr

42 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
59 	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
61 	mcr	p15, 0, r1, c7, c5, 4		@ ISB
75 	mcr	p15, 0, r1, c7, c10, 4		@ DWB - WFI may enter a low-power mode
76 	mcr	p15, 0, r1, c7, c0, 4		@ wait for interrupt
80 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
102 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
103 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
104 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
111 	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
153 	mcr	p15, 0, ip, c7, c14, 0	@ clean+invalidate D cache
154 	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
155 	mcr	p15, 0, ip, c7, c15, 0	@ clean+invalidate cache
156 	mcr	p15, 0, ip, c7, c10, 4	@ drain write buffer
157 	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
159 	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
161 	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
164 	mcr	p15, 0, r1, c2, c0, 0	@ Translation table base 0
165 	mcr	p15, 0, r6, c2, c0, 1	@ Translation table base 1
166 	mcr	p15, 0, ip, c2, c0, 2	@ TTB control register
168 	mcr	p15, 0, r7, c1, c0, 1	@ auxiliary control register
169 	mcr	p15, 0, r8, c1, c0, 2	@ co-processor access control
170 	mcr	p15, 0, ip, c7, c5, 4	@ ISB
200 	ALT_SMP(mcr	p15, 0, r0, c1, c0, 1)
205 	mcr	p15, 0, r0, c7, c14, 0		@ clean+invalidate D cache
206 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
207 	mcr	p15, 0, r0, c7, c15, 0		@ clean+invalidate cache
209 	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
210 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
215 	mcr	p15, 0, r8, c2, c0, 1		@ load TTB1
217 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer and