Lines Matching refs:mcr
41 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
53 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
74 mcr p15, 0, ip, c7, c10, 4 @ drain WB
76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
108 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
110 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
112 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
127 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
147 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
148 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
149 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
165 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
166 mcr p15, 0, r0, c7, c10, 4 @ drain WB
185 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
186 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
187 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
188 mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB
190 mcr p15, 0, r4, c3, c0, 0 @ domain ID
191 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
192 mcr p15, 0, r5, c13, c0, 0 @ PID
201 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
202 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
204 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4