Lines Matching refs:mcr
37 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
66 mcr p15, 0, ip, c7, c10, 4 @ drain WB
68 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
73 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
92 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
98 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
102 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
117 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
137 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
138 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
154 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
155 mcr p15, 0, r0, c7, c10, 4 @ drain WB
162 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
163 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
165 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4