Lines Matching refs:c6
51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
184 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
233 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
276 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
279 mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
280 mcr p15, 0, r0, c6, c4, 0
281 mcr p15, 0, r0, c6, c5, 0
282 mcr p15, 0, r0, c6, c6, 0
283 mcr p15, 0, r0, c6, c7, 0
285 mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
286 mcr p15, 0, r0, c6, c4, 1
287 mcr p15, 0, r0, c6, c5, 1
288 mcr p15, 0, r0, c6, c6, 1
289 mcr p15, 0, r0, c6, c7, 1
292 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
293 mcr p15, 0, r0, c6, c0, 1
298 mcr p15, 0, r3, c6, c1, 0 @ set area 1, RAM
299 mcr p15, 0, r3, c6, c1, 1
304 mcr p15, 0, r3, c6, c2, 0 @ set area 2, ROM/FLASH
305 mcr p15, 0, r3, c6, c2, 1