Lines Matching refs:mcr

53 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
70 mcr p15, 0, ip, c7, c10, 4 @ drain WB
72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
77 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
96 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
98 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
159 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
162 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
166 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
169 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
204 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
205 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
209 mcr p15, 0, r0, c7, c10, 4 @ drain WB
224 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
230 mcr p15, 0, r0, c7, c10, 4 @ drain WB
254 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
258 mcr p15, 0, r0, c7, c10, 4 @ drain WB
274 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
279 mcr p15, 0, r0, c7, c10, 4 @ drain WB
294 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
296 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
301 mcr p15, 0, r0, c7, c10, 4 @ drain WB
336 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
341 mcr p15, 0, r0, c7, c10, 4 @ drain WB
358 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
364 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
365 mcr p15, 0, ip, c7, c10, 4 @ drain WB
366 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
367 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
382 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
384 mcr p15, 0, r0, c7, c10, 4 @ drain WB
403 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
404 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
406 mcr p15, 0, r4, c13, c0, 0 @ PID
407 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
408 mcr p15, 0, r1, c2, c0, 0 @ TTB address
417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
418 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
420 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
426 mcr p15, 7, r0, c15, c0, 0