Lines Matching refs:p15

81 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
84 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
109 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
110 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
112 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
114 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
117 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
128 	mrc	p15, 0, r1, c1, c0, 0		@ Read control register
129 	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
131 	mcr	p15, 0, r2, c1, c0, 0		@ Disable I cache
132 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
133 	mcr	p15, 0, r1, c1, c0, 0		@ Restore ICache enable
143 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
166 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
170 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
175 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
176 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
196 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
197 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
199 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
200 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
203 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
204 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
206 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
207 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
213 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
241 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
242 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
246 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
261 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
266 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
267 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
286 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
288 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
291 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
295 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
311 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
316 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
331 	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
333 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
338 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
373 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
378 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
395 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
399 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean & invalidate D index
403 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
404 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
405 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
406 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
421 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
423 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
433         mcr     p15, 0, r0, c15, c1, 0          @ write TI config register
436 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
437 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
439 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
444 	mcr	p15, 7, r0, c15, c0, 0
449 	mrc	p15, 0, r0, c1, c0		@ get control register v4