Lines Matching refs:r1
114 cpu_to_halt_reg r1, r0
117 str r2, [r3, r1] @ put flow controller in wait event mode
118 ldr r2, [r3, r1]
121 movw r1, 0x1011
122 mov r1, r1, lsl r0
124 str r1, [r3, #0x340] @ put slave CPU in reset
152 mov32 r1, tegra20_iram_start
153 sub r0, r0, r1
154 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
155 add r0, r0, r1
196 mov r1, #(1 << 28)
197 str r1, [r0, #CLK_RESET_SCLK_BURST]
198 str r1, [r0, #CLK_RESET_CCLK_BURST]
199 mov r1, #0
200 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
201 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
203 pll_enable r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
204 pll_enable r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
205 pll_enable r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
215 ldr r1, [r4, r5]
216 str r1, [r7] @ restore the value in pad_save
225 ldr r1, [r7]
226 add r1, r1, #0xff
227 wait_until r1, r7, r9
236 ldr r1, [r0, #EMC_CFG]
237 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP
238 str r1, [r0, #EMC_CFG]
240 mov r1, #0
241 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
242 mov r1, #1
243 str r1, [r0, #EMC_NOP]
244 str r1, [r0, #EMC_NOP]
246 emc_device_mask r1, r0
250 ands r2, r2, r1
253 mov r1, #0 @ unstall all transactions
254 str r1, [r0, #EMC_REQ_CTRL]
292 ldr r1, [r7]
293 add r1, r1, #2
294 wait_until r1, r7, r9
296 store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
297 store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
298 store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
329 cpu_id r1
330 cpu_to_halt_reg r1, r1
331 str r0, [r6, r1]
333 ldr r0, [r6, r1] /* memory barrier */
349 mov32 r1, TEGRA_EMC_BASE @ r1 reserved for emc base addr
352 str r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests
355 ldr r2, [r1, #EMC_EMC_STATUS]
360 str r2, [r1, #EMC_SELF_REF]
362 emc_device_mask r2, r1
365 ldr r3, [r1, #EMC_EMC_STATUS]
379 ldr r1, [r0]
380 str r1, [r4, r5] @ save the content of the addr
382 ldr r1, [r3, r5]
383 str r1, [r0] @ set the save val to the addr