341 #define UTCR1_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
342                 	(((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
344 #define UTCR2_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
345                 	(((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
349 #define UTCR1_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
350                 	(((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
352 #define UTCR2_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
353                 	(((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
480 #define SDCR3_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
481                 	(((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
483 #define SDCR4_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
484                 	(((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
488 #define SDCR3_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
489                 	(((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
491 #define SDCR4_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
492                 	(((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
641 #define MCCR0_AudSmpDiv(Div)    	/*  Audio Sampling rate Divisor    */ \  argument
643                 	((Div)/32 << FShft (MCCR0_ASD))
646 #define MCCR0_CeilAudSmpDiv(Div)	/*  Ceil. of AudSmpDiv [192..4064] */ \  argument
647                 	(((Div) + 31)/32 << FShft (MCCR0_ASD))
654 #define MCCR0_TcmSmpDiv(Div)    	/*  Telecom Sampling rate Divisor  */ \  argument
656                 	((Div)/32 << FShft (MCCR0_TSD))
659 #define MCCR0_CeilTcmSmpDiv(Div)	/*  Ceil. of TcmSmpDiv [512..4064] */ \  argument
660                 	(((Div) + 31)/32 << FShft (MCCR0_TSD))
681 #define MCCR0_ExtClkDiv(Div)    	/*  External Clock Divisor [1..4]  */ \  argument
682                 	(((Div) - 1) << FShft (MCCR0_ECP))
774 #define SSCR0_SerClkDiv(Div)    	/*  Serial Clock Divisor [2..512]  */ \  argument
775                 	(((Div) - 2)/2 << FShft (SSCR0_SCR))
778 #define SSCR0_CeilSerClkDiv(Div)	/*  Ceil. of SerClkDiv [2..512]    */ \  argument
779                 	(((Div) - 1)/2 << FShft (SSCR0_SCR))
1754 #define LCCR3_PixClkDiv(Div)    	/*  Pixel Clock Divisor [6..514]   */ \  argument
1755                 	(((Div) - 4)/2 << FShft (LCCR3_PCD))
1758 #define LCCR3_CeilPixClkDiv(Div)	/*  Ceil. of PixClkDiv [6..514]    */ \  argument
1759                 	(((Div) - 3)/2 << FShft (LCCR3_PCD))
1764 #define LCCR3_ACBsDiv(Div)      	/*  AC Bias clock Divisor [2..512] */ \  argument
1765                 	(((Div) - 2)/2 << FShft (LCCR3_ACB))
1768 #define LCCR3_CeilACBsDiv(Div)  	/*  Ceil. of ACBsDiv [2..512]      */ \  argument
1769                 	(((Div) - 1)/2 << FShft (LCCR3_ACB))