341 #define UTCR1_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
344 #define UTCR2_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
349 #define UTCR1_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
352 #define UTCR2_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
480 #define SDCR3_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
483 #define SDCR4_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
488 #define SDCR3_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
491 #define SDCR4_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
641 #define MCCR0_AudSmpDiv(Div)    	/*  Audio Sampling rate Divisor    */ \  argument
646 #define MCCR0_CeilAudSmpDiv(Div)	/*  Ceil. of AudSmpDiv [192..4064] */ \  argument
654 #define MCCR0_TcmSmpDiv(Div)    	/*  Telecom Sampling rate Divisor  */ \  argument
659 #define MCCR0_CeilTcmSmpDiv(Div)	/*  Ceil. of TcmSmpDiv [512..4064] */ \  argument
681 #define MCCR0_ExtClkDiv(Div)    	/*  External Clock Divisor [1..4]  */ \  argument
774 #define SSCR0_SerClkDiv(Div)    	/*  Serial Clock Divisor [2..512]  */ \  argument
778 #define SSCR0_CeilSerClkDiv(Div)	/*  Ceil. of SerClkDiv [2..512]    */ \  argument
1754 #define LCCR3_PixClkDiv(Div)    	/*  Pixel Clock Divisor [6..514]   */ \  argument
1758 #define LCCR3_CeilPixClkDiv(Div)	/*  Ceil. of PixClkDiv [6..514]    */ \  argument
1764 #define LCCR3_ACBsDiv(Div)      	/*  AC Bias clock Divisor [2..512] */ \  argument
1768 #define LCCR3_CeilACBsDiv(Div)  	/*  Ceil. of ACBsDiv [2..512]      */ \  argument