Lines Matching refs:ccu
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
89 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
90 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
91 <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
92 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
100 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
101 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
102 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
103 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
104 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
116 clocks = <&ccu CLK_CPU>;
265 clocks = <&ccu CLK_AHB_DMA>;
273 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
286 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
300 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
316 clocks = <&ccu CLK_AHB_EMAC>;
335 resets = <&ccu RST_TCON0>;
337 clocks = <&ccu CLK_AHB_LCD0>,
338 <&ccu CLK_TCON0_CH0>,
339 <&ccu CLK_TCON0_CH1>;
385 resets = <&ccu RST_TCON1>;
387 clocks = <&ccu CLK_AHB_LCD1>,
388 <&ccu CLK_TCON1_CH0>,
389 <&ccu CLK_TCON1_CH1>;
434 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
435 <&ccu CLK_DRAM_VE>;
437 resets = <&ccu RST_VE>;
445 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
458 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
469 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
480 clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
491 clocks = <&ccu CLK_AHB_OTG>;
507 clocks = <&ccu CLK_USB_PHY>;
509 resets = <&ccu RST_USB_PHY0>,
510 <&ccu RST_USB_PHY1>,
511 <&ccu RST_USB_PHY2>;
520 clocks = <&ccu CLK_AHB_EHCI0>;
530 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
540 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
548 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
549 <&ccu CLK_PLL_VIDEO0_2X>,
550 <&ccu CLK_PLL_VIDEO1_2X>;
588 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
602 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
610 clocks = <&ccu CLK_AHB_EHCI1>;
620 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
630 clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
632 resets = <&ccu RST_CSI1>;
640 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
650 ccu: clock@1c20000 { label
651 compatible = "allwinner,sun4i-a10-ccu";
670 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
879 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
889 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
898 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
910 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
930 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
956 clocks = <&ccu CLK_APB1_UART0>;
966 clocks = <&ccu CLK_APB1_UART1>;
976 clocks = <&ccu CLK_APB1_UART2>;
986 clocks = <&ccu CLK_APB1_UART3>;
996 clocks = <&ccu CLK_APB1_UART4>;
1006 clocks = <&ccu CLK_APB1_UART5>;
1016 clocks = <&ccu CLK_APB1_UART6>;
1026 clocks = <&ccu CLK_APB1_UART7>;
1034 clocks = <&ccu CLK_APB1_PS20>;
1042 clocks = <&ccu CLK_APB1_PS21>;
1050 clocks = <&ccu CLK_APB1_I2C0>;
1062 clocks = <&ccu CLK_APB1_I2C1>;
1074 clocks = <&ccu CLK_APB1_I2C2>;
1086 clocks = <&ccu CLK_APB1_CAN>;
1103 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1105 resets = <&ccu RST_GPU>;
1107 assigned-clocks = <&ccu CLK_GPU>;
1115 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1116 <&ccu CLK_DRAM_DE_FE0>;
1119 resets = <&ccu RST_DE_FE0>;
1147 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1148 <&ccu CLK_DRAM_DE_FE1>;
1151 resets = <&ccu RST_DE_FE1>;
1179 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1180 <&ccu CLK_DRAM_DE_BE1>;
1183 resets = <&ccu RST_DE_BE1>;
1227 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1228 <&ccu CLK_DRAM_DE_BE0>;
1231 resets = <&ccu RST_DE_BE0>;