Lines Matching refs:assigned
154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
261 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
262 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
285 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
286 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
334 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
335 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
336 assigned-clock-rates = <48000000>;
347 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
348 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
349 assigned-clock-rates = <48000000>;
359 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
360 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
361 assigned-clock-rates = <48000000>;
371 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
372 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
373 assigned-clock-rates = <48000000>;