Lines Matching refs:thread
41 CPU-thread-0 {try to write to addrA}
42 CPU-thread-1 {try to write to addrB}
43 CPU-thread-2 {}
44 CPU-thread-3 {}
45 DEV-thread-0 {read addrA and populate device TLB}
46 DEV-thread-2 {read addrB and populate device TLB}
48 CPU-thread-0 {COW_step0: {mmu_notifier_invalidate_range_start(addrA)}}
49 CPU-thread-1 {COW_step0: {mmu_notifier_invalidate_range_start(addrB)}}
50 CPU-thread-2 {}
51 CPU-thread-3 {}
52 DEV-thread-0 {}
53 DEV-thread-2 {}
55 CPU-thread-0 {COW_step1: {update page table to point to new page for addrA}}
56 CPU-thread-1 {COW_step1: {update page table to point to new page for addrB}}
57 CPU-thread-2 {}
58 CPU-thread-3 {}
59 DEV-thread-0 {}
60 DEV-thread-2 {}
62 CPU-thread-0 {preempted}
63 CPU-thread-1 {preempted}
64 CPU-thread-2 {write to addrA which is a write to new page}
65 CPU-thread-3 {}
66 DEV-thread-0 {}
67 DEV-thread-2 {}
69 CPU-thread-0 {preempted}
70 CPU-thread-1 {preempted}
71 CPU-thread-2 {}
72 CPU-thread-3 {write to addrB which is a write to new page}
73 DEV-thread-0 {}
74 DEV-thread-2 {}
76 CPU-thread-0 {preempted}
77 CPU-thread-1 {COW_step3: {mmu_notifier_invalidate_range_end(addrB)}}
78 CPU-thread-2 {}
79 CPU-thread-3 {}
80 DEV-thread-0 {}
81 DEV-thread-2 {}
83 CPU-thread-0 {preempted}
84 CPU-thread-1 {}
85 CPU-thread-2 {}
86 CPU-thread-3 {}
87 DEV-thread-0 {read addrA from old page}
88 DEV-thread-2 {read addrB from new page}
98 is true even if the thread doing the page table update is preempted right after