Lines Matching refs:GPIO
2 GPIO Driver Interface
5 This document serves as a guide for writers of GPIO chip drivers.
7 Each GPIO controller driver needs to include the following header, which defines
8 the structures used to define a GPIO driver::
16 A GPIO chip handles one or more GPIO lines. To be considered a GPIO chip, the
18 line is not general purpose, it is not GPIO and should not be handled by a
19 GPIO chip. The use case is the indicative: certain lines in a system may be
20 called GPIO but serve a very particular purpose thus not meeting the criteria
22 GPIO and should therefore still be handled by a GPIO chip driver.
24 Inside a GPIO driver, individual GPIO lines are identified by their hardware
28 The hardware GPIO number should be something intuitive to the hardware, for
29 example if a system uses a memory-mapped set of I/O-registers where 32 GPIO
34 This number is purely internal: the hardware number of a particular GPIO
37 On top of this internal number, each GPIO line also needs to have a global
38 number in the integer GPIO namespace so that it can be used with the legacy GPIO
40 assigned), and for each GPIO line the global number will be (base + hardware
46 global numbers 0..63 with one set of GPIO controllers, 64-79 with another type
47 of GPIO controller, and on one particular board 80-95 with an FPGA. The legacy
49 2000-2063 to identify GPIO lines in a bank of I2C GPIO expanders.
55 In the gpiolib framework each GPIO controller is packaged as a "struct
60 - methods to establish GPIO line direction
61 - methods used to access GPIO line values
62 - method to set electrical configuration for a given GPIO line
63 - method to return the IRQ number associated to a given GPIO line
68 - optional label for diagnostics and GPIO chip mapping using platform data
73 devm_gpiochip_add_data(). Removing a GPIO controller should be rare; use
77 exposed by the GPIO interfaces, such as addressing, power management, and more.
78 Chips such as audio codecs will have complex non-GPIO states.
82 NULL or the label associated with that GPIO line when it was requested.
84 Realtime considerations: the GPIO driver should not use spinlock_t or any
86 and direction control callbacks) if it is expected to call GPIO APIs from
91 GPIO electrical configuration
94 GPIO lines can be configured for several electrical modes of operation by using
107 ending up in the pin control back-end "behind" the GPIO controller, usually
109 listed GPIO configurations.
111 If a pin controller back-end is used, the GPIO controller or hardware
112 description needs to provide "GPIO ranges" mapping the GPIO line offsets to pin
116 GPIO lines with debounce support
133 GPIO lines with open drain/source support
154 - Inverse wire-OR on an I/O line, for example a GPIO line, making it possible
185 The desired output signal (e.g. coming directly from some GPIO output register)
196 Some GPIO hardware come in open drain / open source configuration. Some are
216 If this state can not be configured in hardware, i.e. if the GPIO hardware does
217 not support open drain/open source in hardware, the GPIO library will instead
230 GPIO lines with pull up/down resistor support
233 A GPIO line can support pull-up/down using the .set_config() callback. This
235 GPIO line, and this resistor is software controlled.
246 If the GPIO line supports shunting in different resistance values for the
247 pull-up or pull-down resistor, the GPIO chip callback .set_config() will not
248 suffice. For these complex use cases, a combined GPIO chip and pin controller
254 GPIO drivers providing IRQs
257 It is custom that GPIO drivers (GPIO chips) are also providing interrupts,
259 cases the GPIO logic is melded with a SoC's primary interrupt controller.
261 The IRQ portions of the GPIO block are implemented using an irq_chip, using
266 is a combined GPIO+IRQ driver. The basic premise is that gpio_chip and
271 certain GPIO line and should not be relied upon to have been called before
275 callbacks from the GPIO and irq_chip APIs. Do not rely on gpiod_to_irq() having
278 We can divide GPIO irqchips in two broad categories:
280 - CASCADED INTERRUPT CHIPS: this means that the GPIO chip has one common
281 interrupt output line, which is triggered by any enabled GPIO line on that
285 inside the GPIO controller to figure out which line fired it. The irqchip
293 - HIERARCHICAL INTERRUPT CHIPS: this means that each GPIO line has a dedicated
295 to inquire the GPIO hardware to figure out which line has fired, but it
299 Realtime considerations: a realtime compliant GPIO driver should not use
309 Cascaded GPIO irqchips
312 Cascaded GPIO irqchips usually fall in one of three categories:
314 - CHAINED CASCADED GPIO IRQCHIPS: these are usually the type that is embedded on
317 system interrupt controller. This means that the GPIO irqchip handler will
319 disabled. The GPIO irqchip will then end up calling something like this
327 Chained GPIO irqchips typically can NOT set the .can_sleep flag on
335 If required (and if it can't be converted to the nested threaded GPIO irqchip,
352 - GENERIC CHAINED GPIO IRQCHIPS: these are the same as "CHAINED GPIO irqchips",
353 but chained IRQ handlers are not used. Instead GPIO IRQs dispatching is
355 The GPIO irqchip will then end up calling something like this sequence in
359 for each detected GPIO IRQ
364 with IRQ enabled and the same work-around as for "CHAINED GPIO irqchips" can
367 - NESTED THREADED GPIO IRQCHIPS: these are off-chip GPIO expanders and any
368 other GPIO irqchip residing on the other side of a sleeping bus such as I2C
382 The hallmark of threaded GPIO irqchips is that they set the .can_sleep
390 Infrastructure helpers for GPIO irqchips
393 To help out in handling the set-up and management of GPIO irqchips and the
399 GPIO line index:
402 :header: GPIO line offset, Hardware IRQ
411 If some GPIO lines do not have corresponding IRQs, the bitmask valid_mask
418 same time as setting up the rest of the GPIO functionality. The following
650 If there is a need to exclude certain GPIO lines from the IRQ domain handled by
653 .irq.valid_mask with as many bits set as there are GPIO lines in the chip, each
654 bit representing line 0..n-1. Drivers can exclude GPIO lines by clearing bits
673 Since GPIO and irq_chip are orthogonal, we can get conflicts between different
674 use cases. For example a GPIO line used for IRQs should be an input line,
675 it does not make sense to fire interrupts on an output GPIO.
678 resource (a certain GPIO line and register for example) it needs to deny
682 to mark the GPIO as being used as an IRQ::
686 This will prevent the use of non-irq related GPIO APIs until the GPIO IRQ lock
691 When implementing an irqchip inside a GPIO driver, these two functions should
702 In some (fringe) use cases, a driver may be using a GPIO line as input for IRQs,
707 When a GPIO is used as an IRQ signal, then gpiolib also needs to know if
713 This allows drivers to drive the GPIO as an output while the IRQ is
718 When implementing an irqchip inside a GPIO driver, these two functions should
727 Real-Time compliance for GPIO IRQ chips
731 preemption. It is desirable that all irqchips in the GPIO subsystem keep this
743 - Chained GPIO irqchips: ensure spinlock_t or any sleepable APIs are not used
745 - Generic chained GPIO irqchips: take care about generic_handle_irq() calls and
747 - Chained GPIO irqchips: get rid of the chained IRQ handler and use generic irq
750 .disable_locking and handling the locking in the GPIO driver
759 Requesting self-owned GPIO pins
762 Sometimes it is useful to allow a GPIO chip driver to request its own GPIO
763 descriptors through the gpiolib API. A GPIO driver can use the following