Lines Matching refs:assigned

35   assigned-clocks:
39   assigned-clock-parents:
43   assigned-clock-rates:
63   - assigned-clocks
64   - assigned-clock-parents
79         assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
82         assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
83         assigned-clock-rates = <368640000>, <49152000>, <12288000>;
101         assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
102         assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
171             assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
172             assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
173             assigned-clock-rates = <1536000>;