Lines Matching refs:space

17 debug blocks defined within this memory space.
25 	The DCSR space exists in the memory-mapped bus.
44 	range of the DCSR space.
57 This node represents the region of DCSR space allocated to the EPU
91 	offset and length of the DCSR space registers of the device
107 This node represents the region of DCSR space allocated to the NPC
120 	offset and length of the DCSR space registers of the device
122 	The Nexus Port controller occupies two regions in the DCSR space
144 This node represents the region of DCSR space allocated to the NXC
157 	offset and length of the DCSR space registers of the device
168 This node represents the region of DCSR space allocated to
182 	offset and length of the DCSR space registers of the device
184 	The CoreNet Debug controller occupies two regions in the DCSR space
202 This node represents the region of DCSR space allocated to
219 	offset and length of the DCSR space registers of the device
231 This node represents the region of DCSR space allocated to
247 	offset and length of the DCSR space registers of the device
259 This node represents the region of DCSR space allocated to
278 	offset and length of the DCSR space registers of the device
291 This node represents the region of DCSR space allocated to
307 	offset and length of the DCSR space registers of the device
320 This node represents the region of DCSR space allocated to
337 	offset and length of the DCSR space registers of the device
349 This node represents the region of DCSR space allocated to
371 	offset and length of the DCSR space registers of the device