Lines Matching refs:terms

65       CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
73       SELF REFRESH) in terms of number of clock cycles.
79       DQS output data access time from CK_t/CK_c in terms of number of clock
86       Four-bank activate window in terms of number of clock cycles.
92       Mode register set command delay in terms of number of clock cycles.
98       Additional READ-to-READ delay in chip-to-chip cases in terms of number
105       Row active time in terms of number of clock cycles.
111       ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
117       RAS-to-CAS delay in terms of number of clock cycles.
123       Refresh Cycle time in terms of number of clock cycles.
129      READ data latency in terms of number of clock cycles.
135       Row precharge time (all banks) in terms of number of clock cycles.
141       Row precharge time (single banks) in terms of number of clock cycles.
147       Active bank A to active bank B in terms of number of clock cycles.
153       Internal READ to PRECHARGE command delay in terms of number of clock
160       Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
167       WRITE data latency in terms of number of clock cycles.
173       WRITE recovery time in terms of number of clock cycles.
179       Internal WRITE-to-READ command delay in terms of number of clock cycles.
185       Exit power-down to next valid command delay in terms of number of clock
192       SELF REFRESH exit to next valid command delay in terms of number of clock