Lines Matching refs:terms

83       Active bank a to active bank b in terms of number of clock cycles.
90       Internal WRITE-to-READ command delay in terms of number of clock cycles.
97       Exit power-down to next valid command delay in terms of number of clock
104       Internal READ to PRECHARGE command delay in terms of number of clock
111       CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
118       Row precharge time (all banks) in terms of number of clock cycles.
125       RAS-to-CAS delay in terms of number of clock cycles. Obtained from
132       WRITE recovery time in terms of number of clock cycles. Obtained from
139       Row active time in terms of number of clock cycles. Obtained from device
147       SELF REFRESH) in terms of number of clock cycles. Obtained from device
154       Four-bank activate window in terms of number of clock cycles. Obtained