Lines Matching refs:description
14 description: |
26 - description: common_m DSS Master common
27 - description: common_s0 DSS Shared common 0
28 - description: common_s1 DSS Shared common 1
29 - description: common_s2 DSS Shared common 2
30 - description: VIDL1 light video plane 1
31 - description: VIDL2 light video plane 2
32 - description: VID1 video plane 1
33 - description: VID1 video plane 2
34 - description: OVR1 overlay manager for vp1
35 - description: OVR2 overlay manager for vp2
36 - description: OVR3 overlay manager for vp3
37 - description: OVR4 overlay manager for vp4
38 - description: VP1 video port 1
39 - description: VP2 video port 2
40 - description: VP3 video port 3
41 - description: VP4 video port 4
42 - description: WB Write Back
66 - description: fck DSS functional clock
67 - description: vp1 Video Port 1 pixel clock
68 - description: vp2 Video Port 2 pixel clock
69 - description: vp3 Video Port 3 pixel clock
70 - description: vp4 Video Port 4 pixel clock
90 - description: common_m DSS Master common
91 - description: common_s0 DSS Shared common 0
92 - description: common_s1 DSS Shared common 1
93 - description: common_s2 DSS Shared common 2
104 description: phandle to the associated power domain
115 description:
120 description:
125 description:
130 description:
135 description: