Lines Matching refs:peripheral

4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
47 The peripheral clock controller generates clocks for the DDR, ROM, and other
48 peripherals.  The peripheral system clock ("periph_sys") generated by the core
49 clock controller is the input clock to the peripheral clock controller.
53 - reg: Must contain the base address and length of the peripheral clock
58 - clock-names: Must include "periph_sys", the peripheral system clock generated
74 The peripheral general control block generates system interface clocks and
75 resets for various peripherals.  It also contains miscellaneous peripheral
76 control registers.  The system clock ("sys") generated by the peripheral clock
81 - reg: Must contain the base address and length of the peripheral general
86 - clock-names: Must include "sys", the system clock generated by the peripheral