71 static void tegra186_asrc_lock_stream(struct tegra186_asrc *asrc,  in tegra186_asrc_lock_stream()  argument
74 	regmap_write(asrc->regmap,  in tegra186_asrc_lock_stream()
82 	struct tegra186_asrc *asrc = dev_get_drvdata(dev);  in tegra186_asrc_runtime_suspend()  local
84 	regcache_cache_only(asrc->regmap, true);  in tegra186_asrc_runtime_suspend()
85 	regcache_mark_dirty(asrc->regmap);  in tegra186_asrc_runtime_suspend()
92 	struct tegra186_asrc *asrc = dev_get_drvdata(dev);  in tegra186_asrc_runtime_resume()  local
95 	regcache_cache_only(asrc->regmap, false);  in tegra186_asrc_runtime_resume()
102 	regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR,  in tegra186_asrc_runtime_resume()
104 	regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB,  in tegra186_asrc_runtime_resume()
107 	regcache_sync(asrc->regmap);  in tegra186_asrc_runtime_resume()
110 		if (asrc->lane[id].ratio_source !=  in tegra186_asrc_runtime_resume()
114 		regmap_write(asrc->regmap,  in tegra186_asrc_runtime_resume()
117 			asrc->lane[id].int_part);  in tegra186_asrc_runtime_resume()
119 		regmap_write(asrc->regmap,  in tegra186_asrc_runtime_resume()
122 			asrc->lane[id].frac_part);  in tegra186_asrc_runtime_resume()
124 		tegra186_asrc_lock_stream(asrc, id);  in tegra186_asrc_runtime_resume()
130 static int tegra186_asrc_set_audio_cif(struct tegra186_asrc *asrc,  in tegra186_asrc_set_audio_cif()  argument
158 	tegra_set_cif(asrc->regmap, reg, &cif_conf);  in tegra186_asrc_set_audio_cif()
168 	struct tegra186_asrc *asrc = snd_soc_dai_get_drvdata(dai);  in tegra186_asrc_in_hw_params()  local
172 	regmap_write(asrc->regmap,  in tegra186_asrc_in_hw_params()
174 		     asrc->lane[id].input_thresh);  in tegra186_asrc_in_hw_params()
176 	ret = tegra186_asrc_set_audio_cif(asrc, params,  in tegra186_asrc_in_hw_params()
191 	struct tegra186_asrc *asrc = snd_soc_dai_get_drvdata(dai);  in tegra186_asrc_out_hw_params()  local
195 	regmap_write(asrc->regmap,  in tegra186_asrc_out_hw_params()
197 		     asrc->lane[id].output_thresh);  in tegra186_asrc_out_hw_params()
199 	ret = tegra186_asrc_set_audio_cif(asrc, params,  in tegra186_asrc_out_hw_params()
207 	if (asrc->lane[id].hwcomp_disable) {  in tegra186_asrc_out_hw_params()
208 		regmap_update_bits(asrc->regmap,  in tegra186_asrc_out_hw_params()
213 		regmap_update_bits(asrc->regmap,  in tegra186_asrc_out_hw_params()
218 		regmap_write(asrc->regmap,  in tegra186_asrc_out_hw_params()
224 	regmap_update_bits(asrc->regmap,  in tegra186_asrc_out_hw_params()
226 			   1, asrc->lane[id].ratio_source);  in tegra186_asrc_out_hw_params()
228 	if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) {  in tegra186_asrc_out_hw_params()
229 		regmap_write(asrc->regmap,  in tegra186_asrc_out_hw_params()
231 			asrc->lane[id].int_part);  in tegra186_asrc_out_hw_params()
232 		regmap_write(asrc->regmap,  in tegra186_asrc_out_hw_params()
234 			asrc->lane[id].frac_part);  in tegra186_asrc_out_hw_params()
235 		tegra186_asrc_lock_stream(asrc, id);  in tegra186_asrc_out_hw_params()
247 	struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);  in tegra186_asrc_get_ratio_source()  local
250 	ucontrol->value.enumerated.item[0] = asrc->lane[id].ratio_source;  in tegra186_asrc_get_ratio_source()
261 	struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);  in tegra186_asrc_put_ratio_source()  local
265 	asrc->lane[id].ratio_source = ucontrol->value.enumerated.item[0];  in tegra186_asrc_put_ratio_source()
267 	regmap_update_bits_check(asrc->regmap, asrc_private->reg,  in tegra186_asrc_put_ratio_source()
269 				 asrc->lane[id].ratio_source,  in tegra186_asrc_put_ratio_source()
281 	struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);  in tegra186_asrc_get_ratio_int()  local
284 	regmap_read(asrc->regmap,  in tegra186_asrc_get_ratio_int()
286 		    &asrc->lane[id].int_part);  in tegra186_asrc_get_ratio_int()
288 	ucontrol->value.integer.value[0] = asrc->lane[id].int_part;  in tegra186_asrc_get_ratio_int()
299 	struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);  in tegra186_asrc_put_ratio_int()  local
303 	if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) {  in tegra186_asrc_put_ratio_int()
310 	asrc->lane[id].int_part = ucontrol->value.integer.value[0];  in tegra186_asrc_put_ratio_int()
312 	regmap_update_bits_check(asrc->regmap,  in tegra186_asrc_put_ratio_int()
316 				 asrc->lane[id].int_part, &change);  in tegra186_asrc_put_ratio_int()
318 	tegra186_asrc_lock_stream(asrc, id);  in tegra186_asrc_put_ratio_int()
329 	struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);  in tegra186_asrc_get_ratio_frac()  local
332 	regmap_read(asrc->regmap,  in tegra186_asrc_get_ratio_frac()
334 		    &asrc->lane[id].frac_part);  in tegra186_asrc_get_ratio_frac()
336 	ucontrol->value.integer.value[0] = asrc->lane[id].frac_part;  in tegra186_asrc_get_ratio_frac()
347 	struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);  in tegra186_asrc_put_ratio_frac()  local
351 	if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) {  in tegra186_asrc_put_ratio_frac()
358 	asrc->lane[id].frac_part = ucontrol->value.integer.value[0];  in tegra186_asrc_put_ratio_frac()
360 	regmap_update_bits_check(asrc->regmap,  in tegra186_asrc_put_ratio_frac()
364 				 asrc->lane[id].frac_part, &change);  in tegra186_asrc_put_ratio_frac()
366 	tegra186_asrc_lock_stream(asrc, id);  in tegra186_asrc_put_ratio_frac()
377 	struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);  in tegra186_asrc_get_hwcomp_disable()  local
380 	ucontrol->value.integer.value[0] = asrc->lane[id].hwcomp_disable;  in tegra186_asrc_get_hwcomp_disable()
391 	struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);  in tegra186_asrc_put_hwcomp_disable()  local
395 	if (value == asrc->lane[id].hwcomp_disable)  in tegra186_asrc_put_hwcomp_disable()
398 	asrc->lane[id].hwcomp_disable = value;  in tegra186_asrc_put_hwcomp_disable()
409 	struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);  in tegra186_asrc_get_input_threshold()  local
412 	ucontrol->value.integer.value[0] = (asrc->lane[id].input_thresh & 0x3);  in tegra186_asrc_get_input_threshold()
423 	struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);  in tegra186_asrc_put_input_threshold()  local
425 	int value = (asrc->lane[id].input_thresh & ~(0x3)) |  in tegra186_asrc_put_input_threshold()
428 	if (value == asrc->lane[id].input_thresh)  in tegra186_asrc_put_input_threshold()
431 	asrc->lane[id].input_thresh = value;  in tegra186_asrc_put_input_threshold()
442 	struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);  in tegra186_asrc_get_output_threshold()  local
445 	ucontrol->value.integer.value[0] = (asrc->lane[id].output_thresh & 0x3);  in tegra186_asrc_get_output_threshold()
456 	struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);  in tegra186_asrc_put_output_threshold()  local
458 	int value = (asrc->lane[id].output_thresh & ~(0x3)) |  in tegra186_asrc_put_output_threshold()
461 	if (value == asrc->lane[id].output_thresh)  in tegra186_asrc_put_output_threshold()
464 	asrc->lane[id].output_thresh = value;  in tegra186_asrc_put_output_threshold()
473 	struct tegra186_asrc *asrc = dev_get_drvdata(cmpnt->dev);  in tegra186_asrc_widget_event()  local
477 	regmap_write(asrc->regmap,  in tegra186_asrc_widget_event()
967 	struct tegra186_asrc *asrc;  in tegra186_asrc_platform_probe()  local
972 	asrc = devm_kzalloc(dev, sizeof(*asrc), GFP_KERNEL);  in tegra186_asrc_platform_probe()
973 	if (!asrc)  in tegra186_asrc_platform_probe()
976 	dev_set_drvdata(dev, asrc);  in tegra186_asrc_platform_probe()
982 	asrc->regmap = devm_regmap_init_mmio(dev, regs,  in tegra186_asrc_platform_probe()
984 	if (IS_ERR(asrc->regmap)) {  in tegra186_asrc_platform_probe()
986 		return PTR_ERR(asrc->regmap);  in tegra186_asrc_platform_probe()
989 	regcache_cache_only(asrc->regmap, true);  in tegra186_asrc_platform_probe()
991 	regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_CFG,  in tegra186_asrc_platform_probe()
996 		asrc->lane[i].ratio_source = TEGRA186_ASRC_RATIO_SOURCE_SW;  in tegra186_asrc_platform_probe()
997 		asrc->lane[i].int_part = 1;  in tegra186_asrc_platform_probe()
998 		asrc->lane[i].frac_part = 0;  in tegra186_asrc_platform_probe()
999 		asrc->lane[i].hwcomp_disable = 0;  in tegra186_asrc_platform_probe()
1000 		asrc->lane[i].input_thresh =  in tegra186_asrc_platform_probe()
1002 		asrc->lane[i].output_thresh =  in tegra186_asrc_platform_probe()