Lines Matching refs:via_write_reg_mask

44 	via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */  in cle266_set_primary_pll_encoded()
47 	via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */  in cle266_set_primary_pll_encoded()
52 	via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */  in k800_set_primary_pll_encoded()
56 	via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */  in k800_set_primary_pll_encoded()
61 	via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */  in cle266_set_secondary_pll_encoded()
64 	via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */  in cle266_set_secondary_pll_encoded()
69 	via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */  in k800_set_secondary_pll_encoded()
73 	via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */  in k800_set_secondary_pll_encoded()
78 	via_write_reg_mask(VIASR, 0x40, 0x01, 0x01); /* enable reset */  in set_engine_pll_encoded()
82 	via_write_reg_mask(VIASR, 0x40, 0x00, 0x01); /* disable reset */  in set_engine_pll_encoded()
140 	via_write_reg_mask(VIASR, 0x2D, value, 0x30);  in set_primary_pll_state()
158 	via_write_reg_mask(VIASR, 0x2D, value, 0x0C);  in set_secondary_pll_state()
176 	via_write_reg_mask(VIASR, 0x2D, value, 0x03);  in set_engine_pll_state()
194 	via_write_reg_mask(VIASR, 0x1B, value, 0x30);  in set_primary_clock_state()
212 	via_write_reg_mask(VIASR, 0x1B, value, 0xC0);  in set_secondary_clock_state()
249 	via_write_reg_mask(VIACR, 0x6C, data, 0xF0);  in set_primary_clock_source()
255 	via_write_reg_mask(VIACR, 0x6C, data, 0x0F);  in set_secondary_clock_source()