Lines Matching refs:MClk
141 static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk, in nvGetClocks() argument
160 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; in nvGetClocks()
184 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; in nvGetClocks()
213 *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P; in nvGetClocks()
232 *MClk = (N * par->CrystalFreqKHz / M) >> P; in nvGetClocks()
387 unsigned int MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local
389 nvGetClocks(par, &MClk, &NVClk); in nv4UpdateArbitrationSettings()
403 sim_data.mclk_khz = MClk; in nv4UpdateArbitrationSettings()
626 unsigned int MClk, NVClk, cfg1; in nv10UpdateArbitrationSettings() local
628 nvGetClocks(par, &MClk, &NVClk); in nv10UpdateArbitrationSettings()
643 sim_data.mclk_khz = MClk; in nv10UpdateArbitrationSettings()
661 unsigned int MClk, NVClk; in nv30UpdateArbitrationSettings() local
668 nvGetClocks(par, &MClk, &NVClk); in nv30UpdateArbitrationSettings()
684 unsigned int M, N, P, pll, MClk, NVClk, memctrl; in nForceUpdateArbitrationSettings() local
696 MClk = 400000 / uMClkPostDiv; in nForceUpdateArbitrationSettings()
699 pci_read_config_dword(dev, 0x4c, &MClk); in nForceUpdateArbitrationSettings()
700 MClk /= 1000; in nForceUpdateArbitrationSettings()
745 sim_data.mclk_khz = MClk; in nForceUpdateArbitrationSettings()