Lines Matching refs:ufshcd_dme_set
241 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); in exynosauto_ufs_pre_link()
243 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), in exynosauto_ufs_pre_link()
245 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); in exynosauto_ufs_pre_link()
247 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), in exynosauto_ufs_pre_link()
249 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), in exynosauto_ufs_pre_link()
251 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), in exynosauto_ufs_pre_link()
254 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79); in exynosauto_ufs_pre_link()
255 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); in exynosauto_ufs_pre_link()
256 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); in exynosauto_ufs_pre_link()
260 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), in exynosauto_ufs_pre_link()
263 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), in exynosauto_ufs_pre_link()
266 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), in exynosauto_ufs_pre_link()
268 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), in exynosauto_ufs_pre_link()
270 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), in exynosauto_ufs_pre_link()
274 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1); in exynosauto_ufs_pre_link()
277 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); in exynosauto_ufs_pre_link()
279 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); in exynosauto_ufs_pre_link()
281 ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000); in exynosauto_ufs_pre_link()
292 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); in exynosauto_ufs_pre_pwr_change()
293 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); in exynosauto_ufs_pre_pwr_change()
294 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); in exynosauto_ufs_pre_pwr_change()
321 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17); in exynos7_ufs_pre_link()
323 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff); in exynos7_ufs_pre_link()
324 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00); in exynos7_ufs_pre_link()
329 ufshcd_dme_set(hba, in exynos7_ufs_pre_link()
331 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1); in exynos7_ufs_pre_link()
333 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12)); in exynos7_ufs_pre_link()
334 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1); in exynos7_ufs_pre_link()
335 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1); in exynos7_ufs_pre_link()
336 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1); in exynos7_ufs_pre_link()
338 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val); in exynos7_ufs_pre_link()
350 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83); in exynos7_ufs_post_link()
351 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07); in exynos7_ufs_post_link()
352 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), in exynos7_ufs_post_link()
358 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8); in exynos7_ufs_post_link()
378 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1); in exynos7_ufs_post_pwr_change()
382 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1); in exynos7_ufs_post_pwr_change()
491 ufshcd_dme_set(hba, in exynos_ufs_set_pwm_clk_div()
581 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i), in exynos_ufs_config_phy_time_attr()
583 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i), in exynos_ufs_config_phy_time_attr()
585 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
587 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
589 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
591 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
593 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
595 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
600 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i), in exynos_ufs_config_phy_time_attr()
602 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i), in exynos_ufs_config_phy_time_attr()
604 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i), in exynos_ufs_config_phy_time_attr()
606 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
608 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
610 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
612 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
614 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
617 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i), in exynos_ufs_config_phy_time_attr()
633 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
636 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
639 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
642 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
645 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
648 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
655 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
659 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
664 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
671 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
677 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
683 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
704 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE); in exynos_ufs_establish_connt()
707 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID); in exynos_ufs_establish_connt()
708 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), true); in exynos_ufs_establish_connt()
709 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID); in exynos_ufs_establish_connt()
710 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID); in exynos_ufs_establish_connt()
711 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS); in exynos_ufs_establish_connt()
712 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS); in exynos_ufs_establish_connt()
713 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); in exynos_ufs_establish_connt()
761 ufshcd_dme_set(hba, in exynos_ufs_config_sync_pattern_mask()
806 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064); in exynos_ufs_pre_pwr_mode()
807 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224); in exynos_ufs_pre_pwr_mode()
808 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160); in exynos_ufs_pre_pwr_mode()
932 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD), in exynos_ufs_config_unipro()
934 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS), in exynos_ufs_config_unipro()
936 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), in exynos_ufs_config_unipro()
1035 ufshcd_dme_set(hba, in exynos_ufs_post_link()
1040 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY), in exynos_ufs_post_link()
1045 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), in exynos_ufs_post_link()
1049 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), in exynos_ufs_post_link()
1063 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0); in exynos_ufs_post_link()